struct davinci_nand {
target_t *target;
- u8 chipsel; /* chipselect 0..3 == CS2..CS5 */
- u8 eccmode;
+ uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
+ uint8_t eccmode;
/* Async EMIF controller base */
u32 aemif;
/* page i/o for the relevant flavor of hardware ECC */
int (*read_page)(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size);
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
int (*write_page)(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size);
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
};
#define NANDFCR 0x60 /* flash control register */
return 0;
}
-static int davinci_command(struct nand_device_s *nand, u8 command)
+static int davinci_command(struct nand_device_s *nand, uint8_t command)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
return ERROR_OK;
}
-static int davinci_address(struct nand_device_s *nand, u8 address)
+static int davinci_address(struct nand_device_s *nand, uint8_t address)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
/* REVISIT a bit of native code should let block I/O be MUCH faster */
static int davinci_read_block_data(struct nand_device_s *nand,
- u8 *data, int data_size)
+ uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
}
static int davinci_write_block_data(struct nand_device_s *nand,
- u8 *data, int data_size)
+ uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
}
static int davinci_write_page(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
struct davinci_nand *info = nand->controller_priv;
- u8 *ooballoc = NULL;
+ uint8_t *ooballoc = NULL;
int status;
if (!nand->device)
return ERROR_NAND_OPERATION_FAILED;
/* Always write both data and OOB ... we are not "raw" I/O! */
- if (!data)
+ if (!data) {
+ LOG_ERROR("Missing NAND data; try 'nand raw_access enable'\n");
return ERROR_NAND_OPERATION_FAILED;
+ }
/* If we're not given OOB, write 0xff where we don't write ECC codes. */
switch (nand->page_size) {
}
if (!oob) {
ooballoc = malloc(oob_size);
- if (ooballoc)
+ if (!ooballoc)
return ERROR_NAND_OPERATION_FAILED;
oob = ooballoc;
memset(oob, 0x0ff, oob_size);
}
static int davinci_read_page(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
struct davinci_nand *info = nand->controller_priv;
return info->read_page(nand, page, data, data_size, oob, oob_size);
}
-static void davinci_write_pagecmd(struct nand_device_s *nand, u8 cmd, u32 page)
+static void davinci_write_pagecmd(struct nand_device_s *nand, uint8_t cmd, u32 page)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
}
static int davinci_writepage_tail(struct nand_device_s *nand,
- u8 *oob, u32 oob_size)
+ uint8_t *oob, u32 oob_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
- u8 status;
+ uint8_t status;
if (oob_size)
davinci_write_block_data(nand, oob, oob_size);
* All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
*/
static int davinci_write_page_ecc1(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
unsigned oob_offset;
struct davinci_nand *info = nand->controller_priv;
ecc1 = ~ecc1;
/* save correct ECC code into oob data */
- oob[oob_offset++] = (u8)(ecc1);
- oob[oob_offset++] = (u8)(ecc1 >> 8);
- oob[oob_offset++] = (u8)(ecc1 >> 16);
+ oob[oob_offset++] = (uint8_t)(ecc1);
+ oob[oob_offset++] = (uint8_t)(ecc1 >> 8);
+ oob[oob_offset++] = (uint8_t)(ecc1 >> 16);
} while (data_size);
* manufacturer bad block markers are safe. Contrast: old "infix" style.
*/
static int davinci_write_page_ecc4(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
- static const u8 ecc512[] = {
+ static const uint8_t ecc512[] = {
0, 1, 2, 3, 4, /* 5== mfr badblock */
6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
};
- static const u8 ecc2048[] = {
+ static const uint8_t ecc2048[] = {
24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
};
- static const u8 ecc4096[] = {
+ static const uint8_t ecc4096[] = {
48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
};
struct davinci_nand *info = nand->controller_priv;
- const u8 *l;
+ const uint8_t *l;
target_t *target = info->target;
const u32 fcr_addr = info->aemif + NANDFCR;
const u32 ecc4_addr = info->aemif + NAND4BITECC;
* (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
*/
static int davinci_write_page_ecc4infix(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
do {
u32 raw_ecc[4], *p;
- u8 *l;
+ uint8_t *l;
int i;
/* start 4bit ecc on csX */
}
static int davinci_read_page_ecc4infix(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
davinci_write_pagecmd(nand, NAND_CMD_READ0, page);