"trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
static const char get_status_register_err_msg[] = "can't get NAND status";
static uint32_t in_sram_address;
-unsigned char sign_of_sequental_byte_read;
+static unsigned char sign_of_sequental_byte_read;
static int test_iomux_settings (struct target * target, uint32_t value,
uint32_t mask, const char *text);
static int imx31_command (struct nand_device *nand, uint8_t command);
static int imx31_address (struct nand_device *nand, uint8_t address);
-static int imx31_controller_ready (struct nand_device *nand, int tout);
NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
{
return ERROR_NAND_OPERATION_FAILED;
}
-static int imx31_nand_ready (struct nand_device *nand, int timeout)
-{
- return imx31_controller_ready (nand, timeout);
-}
-
static int imx31_reset (struct nand_device *nand)
{
/*
return ERROR_OK;
}
-static int imx31_controller_ready (struct nand_device *nand, int tout)
+static int imx31_nand_ready (struct nand_device *nand, int tout)
{
uint16_t poll_complete_status;
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
.read_data = &imx31_read_data,
.write_page = &imx31_write_page,
.read_page = &imx31_read_page,
- .controller_ready = &imx31_controller_ready,
.nand_ready = &imx31_nand_ready,
};