},
},
+ /* at91samg53n19 */
+ {
+ .chipid_cidr = 0x247e0ae0,
+ .name = "at91samg53n19",
+ .total_flash_size = 512 * 1024,
+ .total_sram_size = 96 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+
+/* .bank[0] = {*/
+ {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+ .controller_address = 0x400e0a00,
+ .flash_wait_states = 6, /* workaround silicon bug */
+ .present = 1,
+ .size_bytes = 512 * 1024,
+ .nsectors = 64,
+ .sector_size = 8192,
+ .page_size = 512,
+ },
+/* .bank[1] = {*/
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ }
+ },
+
/* terminate */
{
.chipid_cidr = 0,
{ 0x3B, "CAP11 Series" },
{ 0x40, "AT91x40 Series" },
{ 0x42, "AT91x42 Series" },
+ { 0x43, "SAMG51 Series"
+ },
+ { 0x47, "SAMG53 Series"
+ },
{ 0x55, "AT91x55 Series" },
{ 0x60, "AT91SAM7Axx Series" },
{ 0x61, "AT91SAM7AQxx Series" },
static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
{
- return (struct sam4_bank_private *)(bank->driver_priv);
+ return bank->driver_priv;
}
/**
return r;
}
-static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
+static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
{
uint32_t adr;
uint32_t status;
}
static int sam4_write(struct flash_bank *bank,
- uint8_t *buffer,
+ const uint8_t *buffer,
uint32_t offset,
uint32_t count)
{