#include "tms470.h"
-static int tms470_register_commands(struct command_context_s *cmd_ctx);
-static int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
-static int tms470_erase(struct flash_bank_s *bank, int first, int last);
-static int tms470_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int tms470_write(struct flash_bank_s *bank, uint8_t * buffer, uint32_t offset, uint32_t count);
-static int tms470_probe(struct flash_bank_s *bank);
-static int tms470_auto_probe(struct flash_bank_s *bank);
-static int tms470_erase_check(struct flash_bank_s *bank);
-static int tms470_protect_check(struct flash_bank_s *bank);
-static int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size);
-
-flash_driver_t tms470_flash = {
- .name = "tms470",
- .register_commands = tms470_register_commands,
- .flash_bank_command = tms470_flash_bank_command,
- .erase = tms470_erase,
- .protect = tms470_protect,
- .write = tms470_write,
- .probe = tms470_probe,
- .auto_probe = tms470_auto_probe,
- .erase_check = tms470_erase_check,
- .protect_check = tms470_protect_check,
- .info = tms470_info
-};
-
-/* ----------------------------------------------------------------------
+/* ----------------------------------------------------------------------
Internal Support, Helpers
---------------------------------------------------------------------- */
-const flash_sector_t TMS470R1A256_SECTORS[] = {
+const struct flash_sector TMS470R1A256_SECTORS[] = {
{0x00000000, 0x00002000, -1, -1},
{0x00002000, 0x00002000, -1, -1},
{0x00004000, 0x00002000, -1, -1},
#define TMS470R1A256_NUM_SECTORS \
(sizeof(TMS470R1A256_SECTORS)/sizeof(TMS470R1A256_SECTORS[0]))
-const flash_sector_t TMS470R1A288_BANK0_SECTORS[] = {
+const struct flash_sector TMS470R1A288_BANK0_SECTORS[] = {
{0x00000000, 0x00002000, -1, -1},
{0x00002000, 0x00002000, -1, -1},
{0x00004000, 0x00002000, -1, -1},
#define TMS470R1A288_BANK0_NUM_SECTORS \
(sizeof(TMS470R1A288_BANK0_SECTORS)/sizeof(TMS470R1A288_BANK0_SECTORS[0]))
-const flash_sector_t TMS470R1A288_BANK1_SECTORS[] = {
+const struct flash_sector TMS470R1A288_BANK1_SECTORS[] = {
{0x00040000, 0x00010000, -1, -1},
{0x00050000, 0x00010000, -1, -1},
{0x00060000, 0x00010000, -1, -1},
#define TMS470R1A288_BANK1_NUM_SECTORS \
(sizeof(TMS470R1A288_BANK1_SECTORS)/sizeof(TMS470R1A288_BANK1_SECTORS[0]))
-const flash_sector_t TMS470R1A384_BANK0_SECTORS[] = {
+const struct flash_sector TMS470R1A384_BANK0_SECTORS[] = {
{0x00000000, 0x00002000, -1, -1},
{0x00002000, 0x00002000, -1, -1},
{0x00004000, 0x00004000, -1, -1},
#define TMS470R1A384_BANK0_NUM_SECTORS \
(sizeof(TMS470R1A384_BANK0_SECTORS)/sizeof(TMS470R1A384_BANK0_SECTORS[0]))
-const flash_sector_t TMS470R1A384_BANK1_SECTORS[] = {
+const struct flash_sector TMS470R1A384_BANK1_SECTORS[] = {
{0x00020000, 0x00008000, -1, -1},
{0x00028000, 0x00008000, -1, -1},
{0x00030000, 0x00008000, -1, -1},
#define TMS470R1A384_BANK1_NUM_SECTORS \
(sizeof(TMS470R1A384_BANK1_SECTORS)/sizeof(TMS470R1A384_BANK1_SECTORS[0]))
-const flash_sector_t TMS470R1A384_BANK2_SECTORS[] = {
+const struct flash_sector TMS470R1A384_BANK2_SECTORS[] = {
{0x00040000, 0x00008000, -1, -1},
{0x00048000, 0x00008000, -1, -1},
{0x00050000, 0x00008000, -1, -1},
/* read and parse the device identification register */
target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
- LOG_INFO("device_ident_reg=0x%08" PRIx32 "", device_ident_reg);
+ LOG_INFO("device_ident_reg = 0x%08" PRIx32 "", device_ident_reg);
if ((device_ident_reg & 7) == 0)
{
bank->chip_width = 32;
bank->bus_width = 32;
- LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
+ LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
part_name,
(int)(silicon_version),
- (technology_family ? "1.8v" : "3.3v"),
+ (technology_family ? "1.8v" : "3.3v"),
(rom_flash ? "rom" : "flash"));
tms470_info->device_ident_reg = device_ident_reg;
static uint32_t keysSet = 0;
static uint32_t flashKeys[4];
-static int tms470_handle_flash_keyset_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(tms470_handle_flash_keyset_command)
{
if (argc > 4)
{
if (keysSet)
{
- command_print(cmd_ctx, "using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
+ command_print(cmd_ctx, "using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
flashKeys[0], flashKeys[1], flashKeys[2], flashKeys[3]);
}
else
static int oscMHz = 12;
-static int tms470_handle_osc_megahertz_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(tms470_handle_osc_megahertz_command)
{
if (argc > 1)
{
static int plldis = 0;
-static int tms470_handle_plldis_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(tms470_handle_plldis_command)
{
if (argc > 1)
{
- command_print(cmd_ctx, "tms470 plldis <0|1>");
+ command_print(cmd_ctx, "tms470 plldis <0 | 1>");
return ERROR_INVALID_ARGUMENTS;
}
else if (argc == 1)
uint32_t fmbbusy;
target_read_u32(target, 0xFFE89C08, &fmbbusy);
- LOG_INFO("tms470 fmbbusy=0x%08" PRIx32 " -> %s", fmbbusy, fmbbusy & 0x8000 ? "unlocked" : "LOCKED");
+ LOG_INFO("tms470 fmbbusy = 0x%08" PRIx32 " -> %s", fmbbusy, fmbbusy & 0x8000 ? "unlocked" : "LOCKED");
return fmbbusy & 0x8000 ? ERROR_OK : ERROR_FLASH_OPERATION_FAILED;
}
*/
target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
- LOG_INFO("tms470 writing fmpkey=0x%08" PRIx32 "", key_set[i]);
+ LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32 "", key_set[i]);
target_write_u32(target, 0xFFE89C0C, key_set[i]);
}
if (ERROR_OK == tms470_check_flash_unlocked(target))
{
- /*
+ /*
* There seems to be a side-effect of reading the FMPKEY
* register in that it re-enables the protection. So we
* re-enable it.
fmmac2 &= ~0x0007;
fmmac2 |= (tms470_info->ordinal & 7);
target_write_u32(target, 0xFFE8BC04, fmmac2);
- LOG_DEBUG("set fmmac2=0x%04" PRIx32 "", fmmac2);
+ LOG_DEBUG("set fmmac2 = 0x%04" PRIx32 "", fmmac2);
/*
* Disable level 1 sector protection by setting bit 15 of FMMAC1.
target_read_u32(target, 0xFFE8BC00, &fmmac1);
fmmac1 |= 0x8000;
target_write_u32(target, 0xFFE8BC00, fmmac1);
- LOG_DEBUG("set fmmac1=0x%04" PRIx32 "", fmmac1);
+ LOG_DEBUG("set fmmac1 = 0x%04" PRIx32 "", fmmac1);
/*
- * FMTCREG=0x2fc0;
+ * FMTCREG = 0x2fc0;
*/
target_write_u32(target, 0xFFE8BC10, 0x2fc0);
- LOG_DEBUG("set fmtcreg=0x2fc0");
+ LOG_DEBUG("set fmtcreg = 0x2fc0");
/*
- * MAXPP=50
+ * MAXPP = 50
*/
target_write_u32(target, 0xFFE8A07C, 50);
- LOG_DEBUG("set fmmaxpp=50");
+ LOG_DEBUG("set fmmaxpp = 50");
/*
- * MAXCP=0xf000+2000
+ * MAXCP = 0xf000 + 2000
*/
target_write_u32(target, 0xFFE8A084, 0xf000 + 2000);
- LOG_DEBUG("set fmmaxcp=0x%04x", 0xf000 + 2000);
+ LOG_DEBUG("set fmmaxcp = 0x%04x", 0xf000 + 2000);
/*
* configure VHV
{
fmmaxep = 0xf000 + 4095;
target_write_u32(target, 0xFFE8A80C, 0x9964);
- LOG_DEBUG("set fmptr3=0x9964");
+ LOG_DEBUG("set fmptr3 = 0x9964");
}
else
{
fmmaxep = 0xa000 + 4095;
target_write_u32(target, 0xFFE8A80C, 0x9b64);
- LOG_DEBUG("set fmptr3=0x9b64");
+ LOG_DEBUG("set fmptr3 = 0x9b64");
}
target_write_u32(target, 0xFFE8A080, fmmaxep);
- LOG_DEBUG("set fmmaxep=0x%04" PRIx32 "", fmmaxep);
+ LOG_DEBUG("set fmmaxep = 0x%04" PRIx32 "", fmmaxep);
/*
- * FMPTR4=0xa000
+ * FMPTR4 = 0xa000
*/
target_write_u32(target, 0xFFE8A810, 0xa000);
- LOG_DEBUG("set fmptr4=0xa000");
+ LOG_DEBUG("set fmptr4 = 0xa000");
/*
* FMPESETUP, delay parameter selected based on clock frequency.
sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * oscMHz / (1 + (glbctrl & 7));
delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
- LOG_DEBUG("set fmpsetup=0x%04" PRIx32 "", (delay << 4) | (delay << 8));
+ LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8));
/*
* FMPVEVACCESS, based on delay.
*/
k = delay | (delay << 8);
target_write_u32(target, 0xFFE8A05C, k);
- LOG_DEBUG("set fmpvevaccess=0x%04" PRIx32 "", k);
+ LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32 "", k);
/*
* FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
*/
k <<= 1;
target_write_u32(target, 0xFFE8A034, k);
- LOG_DEBUG("set fmpchold=0x%04" PRIx32 "", k);
+ LOG_DEBUG("set fmpchold = 0x%04" PRIx32 "", k);
target_write_u32(target, 0xFFE8A040, k);
- LOG_DEBUG("set fmpvevhold=0x%04" PRIx32 "", k);
+ LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32 "", k);
target_write_u32(target, 0xFFE8A024, k);
- LOG_DEBUG("set fmpvevsetup=0x%04" PRIx32 "", k);
+ LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32 "", k);
/*
* FMCVACCESS, based on delay.
*/
k = delay * 16;
target_write_u32(target, 0xFFE8A060, k);
- LOG_DEBUG("set fmcvaccess=0x%04" PRIx32 "", k);
+ LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32 "", k);
/*
* FMCSETUP, based on delay.
*/
k = 0x3000 | delay * 20;
target_write_u32(target, 0xFFE8A020, k);
- LOG_DEBUG("set fmcsetup=0x%04" PRIx32 "", k);
+ LOG_DEBUG("set fmcsetup = 0x%04" PRIx32 "", k);
/*
* FMEHOLD, based on delay.
*/
k = (delay * 20) << 2;
target_write_u32(target, 0xFFE8A038, k);
- LOG_DEBUG("set fmehold=0x%04" PRIx32 "", k);
+ LOG_DEBUG("set fmehold = 0x%04" PRIx32 "", k);
/*
* PWIDTH, CWIDTH, EWIDTH, based on delay.
*/
target_write_u32(target, 0xFFE8A050, delay * 8);
- LOG_DEBUG("set fmpwidth=0x%04" PRIx32 "", delay * 8);
+ LOG_DEBUG("set fmpwidth = 0x%04" PRIx32 "", delay * 8);
target_write_u32(target, 0xFFE8A058, delay * 1000);
- LOG_DEBUG("set fmcwidth=0x%04" PRIx32 "", delay * 1000);
+ LOG_DEBUG("set fmcwidth = 0x%04" PRIx32 "", delay * 1000);
target_write_u32(target, 0xFFE8A054, delay * 5400);
- LOG_DEBUG("set fmewidth=0x%04" PRIx32 "", delay * 5400);
+ LOG_DEBUG("set fmewidth = 0x%04" PRIx32 "", delay * 5400);
return result;
}
uint32_t fmmstat;
target_read_u32(target, 0xFFE8BC0C, &fmmstat);
- LOG_DEBUG("set fmmstat=0x%04" PRIx32 "", fmmstat);
+ LOG_DEBUG("set fmmstat = 0x%04" PRIx32 "", fmmstat);
if (fmmstat & 0x0080)
{
uint32_t flashAddr = bank->base + bank->sectors[sector].offset;
int result = ERROR_OK;
- /*
+ /*
* Set the bit GLBCTRL4 of the GLBCTRL register (in the System
* module) to enable writing to the flash registers }.
*/
target_read_u32(target, 0xFFFFFFDC, &glbctrl);
target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
- LOG_DEBUG("set glbctrl=0x%08" PRIx32 "", glbctrl | 0x10);
+ LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl | 0x10);
/* Force normal read mode. */
target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
target_write_u32(target, 0xFFE89C00, 0);
- LOG_DEBUG("set fmregopt=0x%08x", 0);
+ LOG_DEBUG("set fmregopt = 0x%08x", 0);
(void)tms470_flash_initialize_internal_state_machine(bank);
{
target_read_u32(target, 0xFFE88008, &fmbsea);
target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
- LOG_DEBUG("set fmbsea=0x%04" PRIx32 "", fmbsea | (1 << sector));
+ LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea | (1 << sector));
}
else
{
target_read_u32(target, 0xFFE8800C, &fmbseb);
target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
- LOG_DEBUG("set fmbseb=0x%04" PRIx32 "", fmbseb | (1 << (sector - 16)));
+ LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb | (1 << (sector - 16)));
}
bank->sectors[sector].is_protected = 0;
- /*
- * clear status regiser, sent erase command, kickoff erase
+ /*
+ * clear status regiser, sent erase command, kickoff erase
*/
target_write_u16(target, flashAddr, 0x0040);
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flashAddr);
if (sector < 16)
{
target_write_u32(target, 0xFFE88008, fmbsea);
- LOG_DEBUG("set fmbsea=0x%04" PRIx32 "", fmbsea);
+ LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea);
bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
}
else
{
target_write_u32(target, 0xFFE8800C, fmbseb);
- LOG_DEBUG("set fmbseb=0x%04" PRIx32 "", fmbseb);
+ LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb);
bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
}
target_write_u32(target, 0xFFE89C00, orig_fmregopt);
- LOG_DEBUG("set fmregopt=0x%08" PRIx32 "", orig_fmregopt);
+ LOG_DEBUG("set fmregopt = 0x%08" PRIx32 "", orig_fmregopt);
target_write_u32(target, 0xFFFFFFDC, glbctrl);
- LOG_DEBUG("set glbctrl=0x%08" PRIx32 "", glbctrl);
+ LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl);
if (result == ERROR_OK)
{
return result;
}
-/* ----------------------------------------------------------------------
+/* ----------------------------------------------------------------------
Implementation of Flash Driver Interfaces
---------------------------------------------------------------------- */
if (fmmstat & 0x3ff)
{
- LOG_ERROR("fmstat=0x%04" PRIx32 "", fmmstat);
+ LOG_ERROR("fmstat = 0x%04" PRIx32 "", fmmstat);
LOG_ERROR("Could not program word 0x%04x at address 0x%08" PRIx32 ".", word, addr);
result = ERROR_FLASH_OPERATION_FAILED;
break;
target_read_u32(target, 0xFFE8BC04, &fmmac2);
target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
- /* TCR=0 */
+ /* TCR = 0 */
target_write_u32(target, 0xFFE8BC10, 0x2fc0);
/* clear TEZ in fmbrdy */
target_read_u32(target, 0xFFE88004, &fmbac2);
target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
- /*
+ /*
* The TI primitives inspect the flash memory by reading one 32-bit
* word at a time. Here we read an entire sector and inspect it in
* an attempt to reduce the JTAG overhead.
* [options...]
*/
-static int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
+FLASH_BANK_COMMAND_HANDLER(tms470_flash_bank_command)
{
bank->driver_priv = malloc(sizeof(tms470_flash_bank_t));
return ERROR_OK;
}
+
+struct flash_driver tms470_flash = {
+ .name = "tms470",
+ .register_commands = &tms470_register_commands,
+ .flash_bank_command = &tms470_flash_bank_command,
+ .erase = &tms470_erase,
+ .protect = &tms470_protect,
+ .write = &tms470_write,
+ .probe = &tms470_probe,
+ .auto_probe = &tms470_auto_probe,
+ .erase_check = &tms470_erase_check,
+ .protect_check = &tms470_protect_check,
+ .info = &tms470_info,
+ };
projects / openocd / blobdiff