]> git.sur5r.net Git - openocd/blobdiff - src/target/Makefile.am
cortex a8: add missing error handling
[openocd] / src / target / Makefile.am
index 6d2b76d91190fb9c647aea22f1cf1d2ab902e7ff..ea6d88fce9f005c7b55f5f261cd887fe6e7022aa 100644 (file)
@@ -6,9 +6,8 @@ OOCD_TRACE_FILES =
 endif
 
 AM_CPPFLAGS = \
-       -I$(top_srcdir)/src/helper \
-       -I$(top_srcdir)/src/jtag \
-       -I$(top_srcdir)/src/xsvf
+       -I$(top_srcdir)/src \
+       -I$(top_builddir)/src
 
 BIN2C          = $(top_builddir)/src/helper/bin2char$(EXEEXT_FOR_BUILD)
 
@@ -34,7 +33,9 @@ libtarget_la_SOURCES = \
        $(ARMV7_SRC) \
        $(ARM_MISC_SRC) \
        $(MIPS32_SRC) \
-       avrt.c
+       avrt.c \
+       dsp563xx.c \
+       dsp563xx_once.c
 
 TARGET_CORE_SRC = \
        algorithm.c \
@@ -80,7 +81,10 @@ ARM_DEBUG_SRC = \
        arm_jtag.c \
        arm_disassembler.c \
        arm_simulator.c \
+       arm_semihosting.c \
        arm_adi_v5.c \
+       adi_v5_jtag.c \
+       adi_v5_swd.c \
        embeddedice.c \
        trace.c \
        etb.c \
@@ -98,11 +102,14 @@ MIPS32_SRC = \
 
 noinst_HEADERS = \
        algorithm.h \
+       arm.h \
        arm_dpm.h \
        arm_jtag.h \
        arm_adi_v5.h \
        arm_disassembler.h \
+       arm_opcodes.h \
        arm_simulator.h \
+       arm_semihosting.h \
        arm7_9_common.h \
        arm7tdmi.h \
        arm720t.h \
@@ -118,6 +125,8 @@ noinst_HEADERS = \
        armv7a.h \
        armv7m.h \
        avrt.h \
+       dsp563xx.h \
+       dsp563xx_once.h \
        breakpoints.h \
        cortex_m3.h \
        cortex_a8.h \