cortex a8: add missing error handling

[openocd] / src / target / adi_v5_jtag.c

diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 0d795fb4871a0cc8fc180852c54671095a7521c3..b3687084c8bef37987e2d7a73a14dd1c71dc9f2e 100644 (file)
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -366,15 +366,15 @@ static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
 /** Select the AP register bank matching bits 7:4 of reg. */
 static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
 {
-       uint32_t select = reg & 0x000000F0;
+       uint32_t select_ap_bank = reg & 0x000000F0;
 
-       if (select == dap->ap_bank_value)
+       if (select_ap_bank == dap->ap_bank_value)
                return ERROR_OK;
-       dap->ap_bank_value = select;
+       dap->ap_bank_value = select_ap_bank;
 
-       select |= dap->apsel;
+       select_ap_bank |= dap->apsel;
 
-       return jtag_dp_q_write(dap, DP_SELECT, select);
+       return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
 }
 
 static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
@@ -429,7 +429,7 @@ const struct dap_ops jtag_dp_ops = {
 };
 
 
-const uint8_t swd2jtag_bitseq[] = {
+static const uint8_t swd2jtag_bitseq[] = {
        /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
         * putting both JTAG and SWD logic into reset state.
         */