* *
* Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
* *
+ * Copyright (C) 2009 David Brownell *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
return retval;
target_call_event_callbacks(target,
- old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
+ (old_state == TARGET_DEBUG_RUNNING)
+ ? TARGET_EVENT_DEBUG_HALTED
+ : TARGET_EVENT_HALTED);
}
}
else
static int arm11_assert_reset(struct target *target)
{
- int retval;
struct arm11_common *arm11 = target_to_arm11(target);
- retval = arm11_check_init(arm11);
- if (retval != ERROR_OK)
- return retval;
+ /* optionally catch reset vector */
+ if (target->reset_halt && !(arm11_vcr & 1))
+ arm11_sc7_set_vcr(arm11, arm11_vcr | 1);
+
+ /* Issue some kind of warm reset. */
+ if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+ target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+ } else if (jtag_get_reset_config() & RESET_HAS_SRST) {
+ /* REVISIT handle "pulls" cases, if there's
+ * hardware that needs them to work.
+ */
+ jtag_add_reset(0, 1);
+ } else {
+ LOG_ERROR("%s: how to reset?", target_name(target));
+ return ERROR_FAIL;
+ }
- target->state = TARGET_UNKNOWN;
+ /* registers are now invalid */
+ register_cache_invalidate(arm11->arm.core_cache);
- /* we would very much like to reset into the halted, state,
- * but resetting and halting is second best... */
- if (target->reset_halt)
- {
- CHECK_RETVAL(target_halt(target));
- }
+ target->state = TARGET_RESET;
+ return ERROR_OK;
+}
- /* srst is funny. We can not do *anything* else while it's asserted
- * and it has unkonwn side effects. Make sure no other code runs
- * meanwhile.
- *
- * Code below assumes srst:
- *
- * - Causes power-on-reset (but of what parts of the system?). Bug
- * in arm11?
- *
- * - Messes us TAP state without asserting trst.
- *
- * - There is another bug in the arm11 core. When you generate an access to
- * external logic (for example ddr controller via AHB bus) and that block
- * is not configured (perhaps it is still held in reset), that transaction
- * will never complete. This will hang arm11 core but it will also hang
- * JTAG controller. Nothing, short of srst assertion will bring it out of
- * this.
- *
- * Mysteries:
- *
- * - What should the PC be after an srst reset when starting in the halted
- * state?
- */
+/*
+ * - There is another bug in the arm11 core. (iMX31 specific again?)
+ * When you generate an access to external logic (for example DDR
+ * controller via AHB bus) and that block is not configured (perhaps
+ * it is still held in reset), that transaction will never complete.
+ * This will hang arm11 core but it will also hang JTAG controller.
+ * Nothing short of srst assertion will bring it out of this.
+ */
- jtag_add_reset(0, 1);
- jtag_add_reset(0, 0);
+static int arm11_deassert_reset(struct target *target)
+{
+ struct arm11_common *arm11 = target_to_arm11(target);
+ int retval;
- /* How long do we have to wait? */
- jtag_add_sleep(5000);
+ /* be certain SRST is off */
+ jtag_add_reset(0, 0);
- /* un-mess up TAP state */
+ /* WORKAROUND i.MX31 problems: SRST goofs the TAP, and resets
+ * at least DSCR. OMAP24xx doesn't show that problem, though
+ * SRST-only reset seems to be problematic for other reasons.
+ * (Secure boot sequences being one likelihood!)
+ */
jtag_add_tlr();
- retval = jtag_execute_queue();
- if (retval != ERROR_OK)
- {
- return retval;
+ retval = arm11_poll(target);
+
+ if (target->reset_halt) {
+ if (target->state != TARGET_HALTED) {
+ LOG_WARNING("%s: ran after reset and before halt ...",
+ target_name(target));
+ if ((retval = target_halt(target)) != ERROR_OK)
+ return retval;
+ }
}
- return ERROR_OK;
-}
+ /* maybe restore vector catch config */
+ if (target->reset_halt && !(arm11_vcr & 1))
+ arm11_sc7_set_vcr(arm11, arm11_vcr);
-static int arm11_deassert_reset(struct target *target)
-{
return ERROR_OK;
}
}
case 4: {
+ /* increment: STC p14,c5,[R0],#4 */
+ /* no increment: STC p14,c5,[R0]*/
uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
uint32_t *words = (uint32_t*)buffer;
+ /* "burst" here just means trusting each instruction executes
+ * fully before we run the next one: per-word roundtrips, to
+ * check the Ready flag, are not used.
+ */
if (!burst)
- {
- /* STC p14,c5,[R0],#4 */
- /* STC p14,c5,[R0]*/
- retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
- if (retval != ERROR_OK)
- return retval;
- }
+ retval = arm11_run_instr_data_to_core(arm11,
+ instr, words, count);
else
- {
- /* STC p14,c5,[R0],#4 */
- /* STC p14,c5,[R0]*/
- retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
- if (retval != ERROR_OK)
- return retval;
- }
+ retval = arm11_run_instr_data_to_core_noack(arm11,
+ instr, words, count);
+ if (retval != ERROR_OK)
+ return retval;
break;
}
CHECK_RETVAL(jtag_execute_queue());
- switch (device_id & 0x0FFFF000)
+ /* assume the manufacturer id is ok; check the part # */
+ switch ((device_id >> 12) & 0xFFFF)
{
- case 0x07B36000:
+ case 0x7B36:
type = "ARM1136";
break;
- case 0x07B56000:
+ case 0x7B37:
+ type = "ARM11 MPCore";
+ break;
+ case 0x7B56:
type = "ARM1156";
break;
- case 0x07B76000:
+ case 0x7B76:
arm11->arm.core_type = ARM_MODE_MON;
type = "ARM1176";
break;
default:
- LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
+ LOG_ERROR("unexpected ARM11 ID code");
return ERROR_FAIL;
}
LOG_INFO("found %s", type);
static const struct command_registration arm11_mw_command_handlers[] = {
{
.name = "burst",
- .handler = &arm11_handle_bool_memwrite_burst,
+ .handler = arm11_handle_bool_memwrite_burst,
.mode = COMMAND_ANY,
- .help = "Enable/Disable non-standard but fast burst mode"
- " (default: enabled)",
+ .help = "Display or modify flag controlling potentially "
+ "risky fast burst mode (default: enabled)",
+ .usage = "['enable'|'disable']",
},
{
.name = "error_fatal",
- .handler = &arm11_handle_bool_memwrite_error_fatal,
+ .handler = arm11_handle_bool_memwrite_error_fatal,
.mode = COMMAND_ANY,
- .help = "Terminate program if transfer error was found"
+ .help = "Display or modify flag controlling transfer "
+ "termination on transfer errors"
" (default: enabled)",
+ .usage = "['enable'|'disable']",
},
COMMAND_REGISTRATION_DONE
};
* simulate + breakpoint implementation is broken.
* TEMPORARY! NOT DOCUMENTED! */
.name = "hardware_step",
- .handler = &arm11_handle_bool_hardware_step,
+ .handler = arm11_handle_bool_hardware_step,
.mode = COMMAND_ANY,
.help = "DEBUG ONLY - Hardware single stepping"
" (default: disabled)",
- .usage = "(enable|disable)",
+ .usage = "['enable'|'disable']",
},
{
.name = "memwrite",
},
{
.name = "step_irq_enable",
- .handler = &arm11_handle_bool_step_irq_enable,
+ .handler = arm11_handle_bool_step_irq_enable,
.mode = COMMAND_ANY,
- .help = "Enable interrupts while stepping"
- " (default: disabled)",
+ .help = "Display or modify flag controlling interrupt "
+ "enable while stepping (default: disabled)",
+ .usage = "['enable'|'disable']",
},
{
.name = "vcr",
- .handler = &arm11_handle_vcr,
+ .handler = arm11_handle_vcr,
.mode = COMMAND_ANY,
- .help = "Control (Interrupt) Vector Catch Register",
+ .help = "Display or modify Vector Catch Register",
+ .usage = "[value]",
},
COMMAND_REGISTRATION_DONE
};
projects / openocd / blobdiff