LOG_DEBUG("Bringing target into debug mode");
arm11->dscr |= DSCR_HALT_DBG_MODE;
- arm11_write_DSCR(arm11, arm11->dscr);
+ CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
/* add further reset initialization here */
arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
}
- arm11_sc7_clear_vbw(arm11);
+ CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
}
return ERROR_OK;
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
* but not to issue ITRs(?). The ARMv7 arch spec says it's required
* for executing instructions via ITR.
*/
- arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
+ CHECK_RETVAL(arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr));
/* From the spec:
*/
retval = arm_dpm_read_current_registers(&arm11->dpm);
if (retval != ERROR_OK)
- LOG_ERROR("DPM REG READ -- fail %d", retval);
+ LOG_ERROR("DPM REG READ -- fail");
retval = arm11_run_instr_data_prepare(arm11);
if (retval != ERROR_OK)
/* restore CPSR, PC, and R0 ... after flushing any modified
* registers.
*/
- retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
+ CHECK_RETVAL(arm_dpm_write_dirty_registers(&arm11->dpm, bpwp));
- retval = arm11_bpwp_flush(arm11);
+ CHECK_RETVAL(arm11_bpwp_flush(arm11));
register_cache_invalidate(arm11->arm.core_cache);
/* restore DSCR */
- arm11_write_DSCR(arm11, arm11->dscr);
+ CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
/* maybe restore rDTR */
if (arm11->is_rdtr_saved)
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
/* now processor is ready to RESTART */
enum target_state old_state = target->state;
- arm11_debug_entry(arm11);
+ CHECK_RETVAL(arm11_debug_entry(arm11));
CHECK_RETVAL(
target_call_event_callbacks(target,
static uint32_t
arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
{
- void *value = arm11->arm.core_cache->reg_list[15].value;
+ void *value = arm11->arm.pc->value;
if (!current)
buf_set_u32(value, 0, 32, address);
LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
/* clear breakpoints/watchpoints and VCR*/
- arm11_sc7_clear_vbw(arm11);
+ CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
if (!debug_execution)
target_free_all_working_areas(target);
brp[1].address = ARM11_SC7_BCR0 + brp_num;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
- arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
+ CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
bp->address);
}
if (arm11->vcr)
- arm11_sc7_set_vcr(arm11, arm11->vcr);
+ CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
}
/* activate all watchpoints and breakpoints */
- arm11_leave_debug_state(arm11, true);
+ CHECK_RETVAL(arm11_leave_debug_state(arm11, true));
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
}
/* clear breakpoint */
- arm11_sc7_clear_vbw(arm11);
+ CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
/* save state */
CHECK_RETVAL(arm11_debug_entry(arm11));
/* optionally catch reset vector */
if (target->reset_halt && !(arm11->vcr & 1))
- arm11_sc7_set_vcr(arm11, arm11->vcr | 1);
+ CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1));
/* Issue some kind of warm reset. */
if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
*/
jtag_add_tlr();
- retval = arm11_poll(target);
+ CHECK_RETVAL(arm11_poll(target));
if (target->reset_halt) {
if (target->state != TARGET_HALTED) {
/* maybe restore vector catch config */
if (target->reset_halt && !(arm11->vcr & 1))
- arm11_sc7_set_vcr(arm11, arm11->vcr);
+ CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
return ERROR_OK;
}
{
/* ldrb r1, [r0], #1 */
/* ldrb r1, [r0] */
- arm11_run_instr_no_data1(arm11,
- !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
+ CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
+ !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
uint32_t res;
/* MCR p14,0,R1,c0,c5,0 */
- arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
+ CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
*buffer++ = res;
}
for (size_t i = 0; i < count; i++)
{
/* ldrh r1, [r0], #2 */
- arm11_run_instr_no_data1(arm11,
- !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
+ CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
+ !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
uint32_t res;
/* MCR p14,0,R1,c0,c5,0 */
- arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
+ CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
uint16_t svalue = res;
memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
{
uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
- uint32_t *words = (uint32_t *)buffer;
+ uint32_t *words = (uint32_t *)(void *)buffer;
/* LDC p14,c5,[R0],#4 */
/* LDC p14,c5,[R0] */
- arm11_run_instr_data_from_core(arm11, instr, words, count);
+ CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count));
break;
}
}
*/
static int arm11_write_memory_inner(struct target *target,
uint32_t address, uint32_t size,
- uint32_t count, uint8_t *buffer,
+ uint32_t count, const uint8_t *buffer,
bool no_increment)
{
int retval;
uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
- uint32_t *words = (uint32_t*)buffer;
+ uint32_t *words = (uint32_t*)(void *)buffer;
/* "burst" here just means trusting each instruction executes
* fully before we run the next one: per-word roundtrips, to
static int arm11_write_memory(struct target *target,
uint32_t address, uint32_t size,
- uint32_t count, uint8_t *buffer)
+ uint32_t count, const uint8_t *buffer)
{
/* pointer increment matters only for multi-unit writes ...
* not e.g. to a "reset the chip" controller.
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
static int arm11_bulk_write_memory(struct target *target,
- uint32_t address, uint32_t count, uint8_t *buffer)
+ uint32_t address, uint32_t count, const uint8_t *buffer)
{
if (target->state != TARGET_HALTED)
{
arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
- arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &idcode_field, TAP_DRPAUSE);
/* check DIDR */
arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
- arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
+ arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
* want to know if this core supports Secure Monitor mode.
*/
if (!target_was_examined(target))
- retval = arm11_dpm_init(arm11, didr);
+ CHECK_RETVAL(arm11_dpm_init(arm11, didr));
/* ETM on ARM11 still uses original scanchain 6 access mode */
if (arm11->arm.etm && !target_was_examined(target)) {
*register_get_last_cache_p(&target->reg_cache) =
etm_build_reg_cache(target, &arm11->jtag_info,
arm11->arm.etm);
- retval = etm_setup(target);
+ CHECK_RETVAL(etm_setup(target));
}
target_set_examined(target);
projects / openocd / blobdiff