* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
static void arm11_on_enter_debug_state(arm11_common_t * arm11);
-int arm11_config_memwrite_burst = 1;
-int arm11_config_memwrite_error_fatal = 1;
+bool arm11_config_memwrite_burst = true;
+bool arm11_config_memwrite_error_fatal = true;
u32 arm11_vcr = 0;
ARM11_RC_WDTR,
ARM11_RC_RDTR,
-
ARM11_RC_MAX,
};
/* add further reset initialization here */
+ arm11->simulate_reset_on_next_halt = true;
+
if (*dscr & ARM11_DSCR_CORE_HALTED)
{
+ /** \todo TODO: this needs further scrutiny because
+ * arm11_on_enter_debug_state() never gets properly called
+ */
+
arm11->target->state = TARGET_HALTED;
arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
}
arm11_write_DSCR(arm11, new_dscr);
- /* jtag_execute_queue(); */
-
-
-/*
- DEBUG("SAVE DSCR %08x", R(DSCR));
-
- if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
- DEBUG("SAVE wDTR %08x", R(WDTR));
-*/
-
/* From the spec:
Before executing any instruction in debug state you have to drain the write buffer.
while (1)
{
/* MRC p14,0,R0,c5,c10,0 */
- /* arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000); */
+// arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
/* mcr 15, 0, r0, cr7, cr10, {4} */
arm11_run_instr_no_data1(arm11, 0xee070f9a);
arm11->reg_values[ARM11_RC_PC] -= 8;
}
- /* DEBUG("SAVE PC %08x", R(PC)); */
+ if (arm11->simulate_reset_on_next_halt)
+ {
+ arm11->simulate_reset_on_next_halt = false;
+
+ DEBUG("Reset c1 Control Register");
+
+ /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
+
+ /* MCR p15,0,R0,c1,c0,0 */
+ arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
+
+ }
+
+
arm11_run_instr_data_finish(arm11);
/* MRC p14,0,r?,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
- /* DEBUG("RESTORE R%d %08x", i, R(RX + i)); */
+// DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
}}
arm11_run_instr_data_finish(arm11);
DEBUG("target->state: %s", target_state_strings[target->state]);
+ if (target->state == TARGET_UNKNOWN)
+ {
+ arm11->simulate_reset_on_next_halt = true;
+ }
+
if (target->state == TARGET_HALTED)
{
WARNING("target was already halted");
if (arm11->trst_active)
{
- arm11->halt_requested = 1;
+ arm11->halt_requested = true;
return ERROR_OK;
}
{
FNC_INFO;
-/*
- DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
- current, address, handle_breakpoints, debug_execution);
-*/
+// DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
+// current, address, handle_breakpoints, debug_execution);
arm11_common_t * arm11 = target->arch_info;
if (!current)
R(PC) = address;
- INFO("RESUME PC %08x", R(PC));
+ INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
/* clear breakpoints/watchpoints and VCR*/
arm11_sc7_clear_vbw(arm11);
arm11_sc7_run(arm11, brp, asizeof(brp));
- DEBUG("Add BP %d at %08x", brp_num, bp->address);
+ DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
brp_num++;
}
if (!current)
R(PC) = address;
- INFO("STEP PC %08x", R(PC));
+ INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
/** \todo TODO: Thumb not supported here */
arm11_read_memory_word(arm11, R(PC), &next_instruction);
- /** skip over BKPT */
+ /* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)
{
R(PC) += 4;
arm11->reg_list[ARM11_RC_PC].dirty = 0;
INFO("Skipping BKPT");
}
+ /* skip over Wait for interrupt / Standby */
+ /* mcr 15, 0, r?, cr7, cr0, {4} */
+ else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
+ {
+ R(PC) += 4;
+ arm11->reg_list[ARM11_RC_PC].valid = 1;
+ arm11->reg_list[ARM11_RC_PC].dirty = 0;
+ INFO("Skipping WFI");
+ }
/* ignore B to self */
else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
{
arm11_on_enter_debug_state(arm11);
}
- /* target->state = TARGET_HALTED; */
+// target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_SINGLESTEP;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
jtag_add_sleep(5000);
arm11_common_t * arm11 = target->arch_info;
- arm11->trst_active = 1;
+ arm11->trst_active = true;
#endif
return ERROR_OK;
/** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
arm11->reg_list[ARM11_RC_R1].dirty = 1;
- while (count--)
+ {size_t i;
+ for (i = 0; i < count; i++)
{
/* ldrb r1, [r0], #1 */
arm11_run_instr_no_data1(arm11, 0xe4d01001);
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
*buffer++ = res;
- }
+ }}
+
break;
case 2:
u16 * buf16 = (u16*)buffer;
- while (count--)
+ {size_t i;
+ for (i = 0; i < count; i++)
{
/* ldrh r1, [r0], #2 */
arm11_run_instr_no_data1(arm11, 0xe0d010b2);
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
*buf16++ = res;
- }
+ }}
+
break;
}
switch (size)
{
case 1:
+ {
arm11->reg_list[ARM11_RC_R1].dirty = 1;
- while (count--)
+ {size_t i;
+ for (i = 0; i < count; i++)
{
/* MRC p14,0,r1,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
/* strb r1, [r0], #1 */
arm11_run_instr_no_data1(arm11, 0xe4c01001);
- }
+ }}
+
break;
+ }
case 2:
{
u16 * buf16 = (u16*)buffer;
- while (count--)
+ {size_t i;
+ for (i = 0; i < count; i++)
{
/* MRC p14,0,r1,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
/* strh r1, [r0], #2 */
arm11_run_instr_no_data1(arm11, 0xe0c010b2);
- }
+ }}
+
break;
}
target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
arm11_common_t *arm11 = target->arch_info;
- /* const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index; */
+// const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
reg->valid = 1;
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
(*cache_p) = cache;
- /* armv7m->core_cache = cache; */
- /* armv7m->process_context = cache; */
+// armv7m->core_cache = cache;
+// armv7m->process_context = cache;
size_t i;
ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
{
- ERROR("arm11->reg_values inconsistent (%d %d %d %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
+ ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
exit(-1);
}
-int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, int * var, char * name)
+int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
{
if (argc == 0)
{
case 'F':
case 'd': /* disable */
case 'D':
- *var = 0;
+ *var = false;
break;
case '1': /* 1 */
case 'T':
case 'e': /* enable */
case 'E':
- *var = 1;
+ *var = true;
break;
}
projects / openocd / blobdiff