#ifndef ARM11_H
#define ARM11_H
-#include <target/armv4_5.h>
-#include <target/arm_dpm.h>
+#include "arm.h"
+#include "arm_dpm.h"
#define ARM11_TAP_DEFAULT TAP_INVALID
/** Debug module state. */
struct arm_dpm dpm;
+ struct arm11_sc7_action *bpwp_actions;
+ unsigned bpwp_n;
size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
- size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
size_t free_brps; /**< Number of breakpoints allocated */
uint32_t dscr; /**< Last retrieved DSCR value. */
bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
+ /* Per-core configurable options.
+ * NOTE that several of these boolean options should not exist
+ * once the relevant code is known to work correctly.
+ */
+ bool memwrite_burst;
+ bool memwrite_error_fatal;
+ bool step_irq_enable;
+ bool hardware_step;
+
+ /** Configured Vector Catch Register settings. */
+ uint32_t vcr;
+
struct arm_jtag jtag_info;
};
ARM11_BYPASS = 0x1F,
};
-enum arm11_dscr
-{
-
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
-};
-
enum arm11_sc7
{
ARM11_SC7_NULL = 0,