- fixes issue with reset and arm926ejs core. Thanks Øyvind Harboe

[openocd] / src / target / arm720t.c

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 0a95e1c524c4bf793bf97e28d70ee3fdd2c550a0..05cc30f4cecccbce0827a72794b60ecf276e6cd5 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -63,13 +63,15 @@ target_type_t arm720t_target =
        .assert_reset = arm7_9_assert_reset,
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm720t_soft_reset_halt,
+       .prepare_reset_halt = arm7_9_prepare_reset_halt,
        
        .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
        .read_memory = arm720t_read_memory,
        .write_memory = arm720t_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
-
+       .checksum_memory = arm7_9_checksum_memory,
+       
        .run_algorithm = armv4_5_run_algorithm,
 
        .add_breakpoint = arm7_9_add_breakpoint,
@@ -96,7 +98,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
        
        jtag_add_end_state(TAP_PD);
        arm_jtag_scann(jtag_info, 0xf);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
                
        fields[0].device = jtag_info->chain_pos;
        fields[0].num_bits = 1;
@@ -125,7 +127,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
        fields[1].in_check_value = NULL;
        fields[1].in_check_mask = NULL;
        
-       jtag_add_dr_scan(2, fields, -1);
+       jtag_add_dr_scan(2, fields, -1, NULL);
 
        if (clock)
                jtag_add_runtest(0, -1);
@@ -138,7 +140,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
        else
                DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 #else
-               DEBUG("out: %8.8x, instruction: %i, clock: %i", in, out, instruction, clock);
+               DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 #endif
 
        return ERROR_OK;
@@ -240,8 +242,8 @@ void arm720t_post_debug_entry(target_t *target)
        arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
        /* save i/d fault status and address register */
-       arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr);
-       arm720t_read_cp15(target, 0xee160f10, &arm720t->far);
+       arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+       arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
        jtag_execute_queue();
 }
 
@@ -253,8 +255,8 @@ void arm720t_pre_restore_context(target_t *target)
        arm720t_common_t *arm720t = arm7tdmi->arch_info;
        
        /* restore i/d fault status and address register */
-       arm720t_write_cp15(target, 0xee050f10, arm720t->fsr);
-       arm720t_write_cp15(target, 0xee060f10, arm720t->far);
+       arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
+       arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 }
 
 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
@@ -371,7 +373,7 @@ int arm720t_soft_reset_halt(struct target_s *target)
                target->type->halt(target);
        }
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
+       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
        {
                embeddedice_read_reg(dbg_stat);
                jtag_execute_queue();