Uwe Hermann tightned up comments, etc. to follow OpenOCD policy

[openocd] / src / target / arm720t.c

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 1b809e6dbf4af8dfe52f918fb572b9d622fab2c4..2c7e2aea3495bb09f688952475bbfb3b2028b594 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -44,7 +44,7 @@ int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd,
 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm720t_quit();
-int arm720t_arch_state(struct target_s *target, char *buf, int buf_size);
+int arm720t_arch_state(struct target_s *target);
 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int arm720t_soft_reset_halt(struct target_s *target);
@@ -63,13 +63,15 @@ target_type_t arm720t_target =
        .assert_reset = arm7_9_assert_reset,
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm720t_soft_reset_halt,
+       .prepare_reset_halt = arm7_9_prepare_reset_halt,
        
        .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
        .read_memory = arm720t_read_memory,
        .write_memory = arm720t_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
-
+       .checksum_memory = arm7_9_checksum_memory,
+       
        .run_algorithm = armv4_5_run_algorithm,
 
        .add_breakpoint = arm7_9_add_breakpoint,
@@ -96,7 +98,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
        
        jtag_add_end_state(TAP_PD);
        arm_jtag_scann(jtag_info, 0xf);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
                
        fields[0].device = jtag_info->chain_pos;
        fields[0].num_bits = 1;
@@ -240,8 +242,8 @@ void arm720t_post_debug_entry(target_t *target)
        arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
        /* save i/d fault status and address register */
-       arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr);
-       arm720t_read_cp15(target, 0xee160f10, &arm720t->far);
+       arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+       arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
        jtag_execute_queue();
 }
 
@@ -253,8 +255,8 @@ void arm720t_pre_restore_context(target_t *target)
        arm720t_common_t *arm720t = arm7tdmi->arch_info;
        
        /* restore i/d fault status and address register */
-       arm720t_write_cp15(target, 0xee050f10, arm720t->fsr);
-       arm720t_write_cp15(target, 0xee060f10, arm720t->far);
+       arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
+       arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 }
 
 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
@@ -295,7 +297,7 @@ int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar
        return ERROR_OK;
 }
 
-int arm720t_arch_state(struct target_s *target, char *buf, int buf_size)
+int arm720t_arch_state(struct target_s *target)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -313,8 +315,7 @@ int arm720t_arch_state(struct target_s *target, char *buf, int buf_size)
                exit(-1);
        }
        
-       snprintf(buf, buf_size,
-                       "target halted in %s state due to %s, current mode: %s\n"
+       USER("target halted in %s state due to %s, current mode: %s\n"
                        "cpsr: 0x%8.8x pc: 0x%8.8x\n"
                        "MMU: %s, Cache: %s",
                         armv4_5_state_strings[armv4_5->core_state],
@@ -371,7 +372,7 @@ int arm720t_soft_reset_halt(struct target_s *target)
                target->type->halt(target);
        }
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
+       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
        {
                embeddedice_read_reg(dbg_stat);
                jtag_execute_queue();