retire daemon_startup

[openocd] / src / target / arm720t.c

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 6b2e2151e3c4026c00199169a847033eb60916e1..cc45c9e61f2e1ba5ae146946588a1892ca121b89 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -63,7 +63,6 @@ target_type_t arm720t_target =
        .assert_reset = arm7_9_assert_reset,
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm720t_soft_reset_halt,
-       .prepare_reset_halt = arm7_9_prepare_reset_halt,
        
        .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
@@ -71,6 +70,7 @@ target_type_t arm720t_target =
        .write_memory = arm720t_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
        .checksum_memory = arm7_9_checksum_memory,
+       .blank_check_memory = arm7_9_blank_check_memory,
        
        .run_algorithm = armv4_5_run_algorithm,
 
@@ -82,6 +82,7 @@ target_type_t arm720t_target =
        .register_commands = arm720t_register_commands,
        .target_command = arm720t_target_command,
        .init_target = arm720t_init_target,
+       .examine = arm7tdmi_examine,
        .quit = arm720t_quit
 };
 
@@ -365,14 +366,28 @@ int arm720t_soft_reset_halt(struct target_s *target)
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
        arm720t_common_t *arm720t = arm7tdmi->arch_info;
+       int i;
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
        
-       target->type->halt(target);
+       target_halt(target);
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+       for (i=0; i<10; i++)
        {
-               embeddedice_read_reg(dbg_stat);
-               jtag_execute_queue();
+               if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+               {
+                       embeddedice_read_reg(dbg_stat);
+                       jtag_execute_queue();
+               } else
+               {
+                       break;
+               }
+               /* do not eat all CPU, time out after 1 se*/
+               usleep(100*1000);
+       }
+       if (i==10)
+       {
+               LOG_ERROR("Failed to halt CPU after 1 sec");
+               return ERROR_TARGET_TIMEOUT;
        }
        
        target->state = TARGET_HALTED;