target read/write is no longer attempted for target_xxx() functions when the target...

[openocd] / src / target / arm7_9_common.c

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 4e14497de0acd3bfab4c3e0b9fe7388a8eac5fa7..d3445257da46688f5e8d0ad9caefca34cf61b0f8 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -649,11 +649,14 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
 int arm7_9_handle_target_request(void *priv)
 {
        target_t *target = priv;
+       if (!target->type->examined)
+               return ERROR_OK;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm_jtag_t *jtag_info = &arm7_9->jtag_info; 
        reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
        
+       
        if (!target->dbg_msg_enabled)
                return ERROR_OK;
                
@@ -736,7 +739,7 @@ int arm7_9_poll(target_t *target)
 /*
   Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
   in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
-  while the core is held in reset. It isn't possible to program the halt
+  while the core is held in reset(SRST). It isn't possible to program the halt
   condition once reset was asserted, hence a hook that allows the target to set
   up its reset-halt condition prior to asserting reset.
 */
@@ -753,38 +756,30 @@ int arm7_9_assert_reset(target_t *target)
                return ERROR_FAIL;
        }
 
-       /*
-        * Some targets do not support communication while TRST is asserted. We need to
-        * set up the reset vector catch here.
-        * 
-        * If TRST is in use, then these settings will be reset anyway, so setting them
-        * here is harmless.  
-        */
-       if (arm7_9->has_vector_catch)
-       {
-               /* program vector catch register to catch reset vector */
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
-       }
-       else
+       if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
        {
-               /* program watchpoint unit to match on reset vector address */
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
+               /*
+                * Some targets do not support communication while SRST is asserted. We need to
+                * set up the reset vector catch here.
+                * 
+                * If TRST is asserted, then these settings will be reset anyway, so setting them
+                * here is harmless.  
+                */
+               if (arm7_9->has_vector_catch)
+               {
+                       /* program vector catch register to catch reset vector */
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
+               }
+               else
+               {
+                       /* program watchpoint unit to match on reset vector address */
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
+               }
        }
 
-       /* we can't know what state the target is in as we might e.g.
-        * be resetting after a power dropout, so we need to issue a tms/srst
-        */
-       
-       
-       /* assert SRST and TRST */
-       /* system would get ouf sync if we didn't reset test-logic, too */
-       jtag_add_reset(1, 1);
-       
-       jtag_add_sleep(5000);
-
        /* here we should issue a srst only, but we may have to assert trst as well */
        if (jtag_reset_config & RESET_SRST_PULLS_TRST)
        {
@@ -867,7 +862,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
        int i;
        int retval;
        
-       if ((retval=target->type->halt(target))!=ERROR_OK)
+       if ((retval=target_halt(target))!=ERROR_OK)
                return retval;
        
        for (i=0; i<10; i++)
@@ -963,6 +958,15 @@ int arm7_9_halt(target_t *target)
                        LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
                        return ERROR_TARGET_FAILURE;
                }
+               else
+               {
+                       /* we came here in a reset_halt or reset_init sequence
+                        * debug entry was already prepared in arm7_9_prepare_reset_halt()
+                        */
+                       target->debug_reason = DBG_REASON_DBGRQ;
+                       
+                       return ERROR_OK; 
+               }
        }
 
        if (arm7_9->use_dbgrq)
@@ -2167,11 +2171,11 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
                }
        }
        
-       target->type->halt(target);
+       target_halt(target);
        
        for (i=0; i<100; i++)
        {
-               target->type->poll(target);
+               target_poll(target);
                if (target->state == TARGET_HALTED)
                        break;
                usleep(1000); /* sleep 1ms */