target read/write is no longer attempted for target_xxx() functions when the target...

[openocd] / src / target / arm7_9_common.c

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index d77f2000279abbd6e619bf472062b80dfddf0f77..d3445257da46688f5e8d0ad9caefca34cf61b0f8 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -649,11 +649,14 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
 int arm7_9_handle_target_request(void *priv)
 {
        target_t *target = priv;
+       if (!target->type->examined)
+               return ERROR_OK;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm_jtag_t *jtag_info = &arm7_9->jtag_info; 
        reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
        
+       
        if (!target->dbg_msg_enabled)
                return ERROR_OK;
                
@@ -777,16 +780,6 @@ int arm7_9_assert_reset(target_t *target)
                }
        }
 
-       /* we can't know what state the target is in as we might e.g.
-        * be resetting after a power dropout, so we need to issue a tms/srst
-        */
-       
-       /* assert SRST and TRST */
-       /* system would get ouf sync if we didn't reset test-logic, too */
-       jtag_add_reset(1, 1);
-       
-       jtag_add_sleep(5000);
-
        /* here we should issue a srst only, but we may have to assert trst as well */
        if (jtag_reset_config & RESET_SRST_PULLS_TRST)
        {
@@ -869,7 +862,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
        int i;
        int retval;
        
-       if ((retval=target->type->halt(target))!=ERROR_OK)
+       if ((retval=target_halt(target))!=ERROR_OK)
                return retval;
        
        for (i=0; i<10; i++)
@@ -965,6 +958,15 @@ int arm7_9_halt(target_t *target)
                        LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
                        return ERROR_TARGET_FAILURE;
                }
+               else
+               {
+                       /* we came here in a reset_halt or reset_init sequence
+                        * debug entry was already prepared in arm7_9_prepare_reset_halt()
+                        */
+                       target->debug_reason = DBG_REASON_DBGRQ;
+                       
+                       return ERROR_OK; 
+               }
        }
 
        if (arm7_9->use_dbgrq)
@@ -2169,11 +2171,11 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
                }
        }
        
-       target->type->halt(target);
+       target_halt(target);
        
        for (i=0; i<100; i++)
        {
-               target->type->poll(target);
+               target_poll(target);
                if (target->state == TARGET_HALTED)
                        break;
                usleep(1000); /* sleep 1ms */