{
if (breakpoint->length == 4)
{
+ u32 verify = 0xffffffff;
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
+
+ target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
+ if (verify != arm7_9->arm_bkpt)
+ {
+ ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
+ return ERROR_OK;
+ }
}
else
{
+ u16 verify = 0xffff;
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
+
+ target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
+ if (verify != arm7_9->thumb_bkpt)
+ {
+ ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
+ return ERROR_OK;
+ }
}
breakpoint->set = 1;
}
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
- target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+ u32 current_instr;
+ /* check that user program as not modified breakpoint instruction */
+ target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr);
+ if (current_instr==arm7_9->arm_bkpt)
+ target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
}
else
{
- target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+ u16 current_instr;
+ /* check that user program as not modified breakpoint instruction */
+ target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr);
+ if (current_instr==arm7_9->thumb_bkpt)
+ target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
}
breakpoint->set = 0;
}
int arm7_9_execute_fast_sys_speed(struct target_s *target)
{
- u8 check_value[4], check_mask[4];
+ static int set=0;
+ static u8 check_value[4], check_mask[4];
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
jtag_add_end_state(TAP_RTI);
arm_jtag_set_instr(jtag_info, 0x4, NULL);
- /* check for DBGACK and SYSCOMP set (others don't care) */
- buf_set_u32(check_value, 0, 32, 0x9);
- buf_set_u32(check_mask, 0, 32, 0x9);
+ if (!set)
+ {
+ /* check for DBGACK and SYSCOMP set (others don't care) */
+
+ /* NB! These are constants that must be available until after next jtag_execute() and
+ we evaluate the values upon first execution in lieu of setting up these constants
+ during early setup.
+ */
+ buf_set_u32(check_value, 0, 32, 0x9);
+ buf_set_u32(check_mask, 0, 32, 0x9);
+ set=1;
+ }
/* read debug status register */
embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
+ if (!target->dbg_msg_enabled)
+ return ERROR_OK;
+
if (target->state == TARGET_RUNNING)
{
/* read DCC control register */
return ERROR_OK;
}
-enum target_state arm7_9_poll(target_t *target)
+int arm7_9_poll(target_t *target)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
embeddedice_read_reg(dbg_stat);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
- switch (retval)
- {
- case ERROR_JTAG_QUEUE_FAILED:
- ERROR("JTAG queue failed while reading EmbeddedICE status register");
- exit(-1);
- break;
- default:
- break;
- }
+ return retval;
}
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
{
DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
- if ((target->state == TARGET_UNKNOWN))
+ if (target->state == TARGET_UNKNOWN)
{
- WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
target->state = TARGET_RUNNING;
+ WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
}
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
}
+ if (target->state != TARGET_HALTED)
+ {
+ WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
+ }
}
else
{
target->state = TARGET_RUNNING;
}
- return target->state;
+ return ERROR_OK;
}
int arm7_9_assert_reset(target_t *target)
{
if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
{
- WARNING("srst resets test logic, too");
retval = jtag_add_reset(1, 1);
}
}
{
if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
{
- WARNING("srst resets test logic, too");
retval = jtag_add_reset(1, 1);
}
}
/* r0 and r15 (pc) have to be restored later */
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
if ((retval = jtag->execute_queue()) != ERROR_OK)
return retval;
else
{
ERROR("BUG: dirty register '%s', but no valid data", reg->name);
- exit(-1);
}
}
}
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
breakpoint_t *breakpoint = target->breakpoints;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+ int err;
DEBUG("-");
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
- arm7_9_execute_sys_speed(target);
+ err = arm7_9_execute_sys_speed(target);
DEBUG("disable single-step");
arm7_9->disable_single_step(target);
-
+
+ if (err != ERROR_OK)
+ {
+ arm7_9_set_breakpoint(target, breakpoint);
+ target->state = TARGET_UNKNOWN;
+ return err;
+ }
+
arm7_9_debug_entry(target);
DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
-
+
DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
arm7_9_set_breakpoint(target, breakpoint);
}
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
breakpoint_t *breakpoint = NULL;
+ int err;
if (target->state != TARGET_HALTED)
{
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
- arm7_9_execute_sys_speed(target);
+ err = arm7_9_execute_sys_speed(target);
arm7_9->disable_single_step(target);
/* registers are now invalid */
armv4_5_invalidate_core_regs(target);
- arm7_9_debug_entry(target);
+ if (err != ERROR_OK)
+ {
+ target->state = TARGET_UNKNOWN;
+ } else {
+ arm7_9_debug_entry(target);
+ target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ DEBUG("target stepped");
+ }
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
-
if (breakpoint)
arm7_9_set_breakpoint(target, breakpoint);
- DEBUG("target stepped");
-
- return ERROR_OK;
+ return err;
}
}
for (i=0; i<=last_reg; i++)
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
arm7_9->read_xpsr(target, &cpsr, 0);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while reading cpsr");
- exit(-1);
+ return ERROR_TARGET_DATA_ABORT;
}
if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
int retval;
int last_reg = 0;
+#ifdef _DEBUG_ARM7_9_
DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
+#endif
if (target->state != TARGET_HALTED)
{
embeddedice_store_reg(dbg_ctrl);
for (i=0; i<=last_reg; i++)
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
arm7_9->read_xpsr(target, &cpsr, 0);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while reading cpsr");
- exit(-1);
+ return ERROR_TARGET_DATA_ABORT;
}
if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
projects / openocd / blobdiff