return ERROR_OK;
}
-enum target_state arm7_9_poll(target_t *target)
+int arm7_9_poll(target_t *target)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
embeddedice_read_reg(dbg_stat);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
- switch (retval)
- {
- case ERROR_JTAG_QUEUE_FAILED:
- ERROR("JTAG queue failed while reading EmbeddedICE status register");
- exit(-1);
- break;
- default:
- break;
- }
+ return retval;
}
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
{
DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
- if ((target->state == TARGET_UNKNOWN))
+ if (target->state == TARGET_UNKNOWN)
{
- WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
target->state = TARGET_RUNNING;
+ WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
}
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
}
+ if (target->state != TARGET_HALTED)
+ {
+ WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
+ }
}
else
{
target->state = TARGET_RUNNING;
}
- return target->state;
+ return ERROR_OK;
}
int arm7_9_assert_reset(target_t *target)
{
if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
{
- WARNING("srst resets test logic, too");
retval = jtag_add_reset(1, 1);
}
}
{
if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
{
- WARNING("srst resets test logic, too");
retval = jtag_add_reset(1, 1);
}
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
- if ((retval = jtag->execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
if (arm7_9->post_debug_entry)
else
{
ERROR("BUG: dirty register '%s', but no valid data", reg->name);
- exit(-1);
}
}
}
arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
- for (i = 0; i < count; i++)
+ int little=target->endianness==TARGET_LITTLE_ENDIAN;
+ if (count>2)
{
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
- buffer += 4;
+ /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
+ core function repeated.
+ */
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ buffer+=4;
+
+ embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
+ u8 reg_addr = ice_reg->addr & 0x1f;
+ int chain_pos = ice_reg->jtag_info->chain_pos;
+ /* we want the compiler to duplicate the code, which it does not
+ * do automatically.
+ */
+ if (little)
+ {
+ for (i = 1; i < count - 1; i++)
+ {
+ embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+ buffer += 4;
+ }
+ } else
+ {
+ for (i = 1; i < count - 1; i++)
+ {
+ embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+ buffer += 4;
+ }
+ }
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ } else
+ {
+ for (i = 0; i < count; i++)
+ {
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ buffer += 4;
+ }
}
target->type->halt(target);