fix xscale icache and dcache commands

[openocd] / src / target / arm7_9_common.c

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 2176729182b98d98f5e76de0fac331873b265a1e..f9deb831090ff53273f2a0c05e5df0b87070f15c 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2834,54 +2834,32 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
        return ERROR_OK;
 }
 
-COMMAND_HANDLER(handle_arm7_9_semihosting_command)
+int arm7_9_setup_semihosting(struct target *target, int enable)
 {
-       struct target *target = get_current_target(CMD_CTX);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
        if (!is_arm7_9(arm7_9))
        {
-               command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
+               LOG_USER("current target isn't an ARM7/ARM9 target");
                return ERROR_TARGET_INVALID;
        }
 
-       if (CMD_ARGC > 0)
-       {
-               int semihosting;
-
-               COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
-
-               if (!target_was_examined(target))
-               {
-                       LOG_ERROR("Target not examined yet");
-                       return ERROR_FAIL;
-               }
-
-               if (arm7_9->has_vector_catch) {
-                       struct reg *vector_catch = &arm7_9->eice_cache
-                                       ->reg_list[EICE_VEC_CATCH];
-
-                       if (!vector_catch->valid)
-                               embeddedice_read_reg(vector_catch);
-                       buf_set_u32(vector_catch->value, 2, 1, semihosting);
-                       embeddedice_store_reg(vector_catch);
-               } else {
-                       /* TODO: allow optional high vectors and/or BKPT_HARD */
-                       if (semihosting)
-                               breakpoint_add(target, 8, 4, BKPT_SOFT);
-                       else
-                               breakpoint_remove(target, 8); 
-               }
-
-               /* FIXME never let that "catch" be dropped! */
-               arm7_9->armv4_5_common.is_semihosting = semihosting;
+       if (arm7_9->has_vector_catch) {
+               struct reg *vector_catch = &arm7_9->eice_cache
+                               ->reg_list[EICE_VEC_CATCH];
 
+               if (!vector_catch->valid)
+                       embeddedice_read_reg(vector_catch);
+               buf_set_u32(vector_catch->value, 2, 1, enable);
+               embeddedice_store_reg(vector_catch);
+       } else {
+               /* TODO: allow optional high vectors and/or BKPT_HARD */
+               if (enable)
+                       breakpoint_add(target, 8, 4, BKPT_SOFT);
+               else
+                       breakpoint_remove(target, 8);
        }
 
-       command_print(CMD_CTX, "semihosting is %s",
-                       arm7_9->armv4_5_common.is_semihosting
-                       ? "enabled" : "disabled");
-
        return ERROR_OK;
 }
 
@@ -2906,6 +2884,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
        armv4_5->read_core_reg = arm7_9_read_core_reg;
        armv4_5->write_core_reg = arm7_9_write_core_reg;
        armv4_5->full_context = arm7_9_full_context;
+       armv4_5->setup_semihosting = arm7_9_setup_semihosting;
 
        retval = arm_init_arch_info(target, armv4_5);
        if (retval != ERROR_OK)
@@ -2939,13 +2918,6 @@ static const struct command_registration arm7_9_any_command_handlers[] = {
                .usage = "['enable'|'disable']",
                .help = "use DCC downloads for larger memory writes",
        },
-       {
-               "semihosting",
-               .handler = handle_arm7_9_semihosting_command,
-               .mode = COMMAND_EXEC,
-               .usage = "['enable'|'disable']",
-               .help = "activate support for semihosting operations",
-       },
        COMMAND_REGISTRATION_DONE
 };
 const struct command_registration arm7_9_command_handlers[] = {