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xscale: use register_commands()
[openocd] / src / target / arm920t.c
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 8a03554f62cb175c8082852c784438b145c3865c..1e6019cb1c4ff49ca4c7cb604572d9f5df60d7f5 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -212,10 +212,11 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 static int arm920t_read_cp15_interpreted(struct target *target,
                uint32_t cp15_opcode, uint32_t address, uint32_t *value)
 {
-       struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_armv4_5(target);
        uint32_t* regs_p[1];
        uint32_t regs[2];
        uint32_t cp15c15 = 0x0;
+       struct reg *r = armv4_5->core_cache->reg_list;
 
        /* load address into R1 */
        regs[1] = address;
@@ -247,8 +248,8 @@ static int arm920t_read_cp15_interpreted(struct target *target,
        if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
 
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
+       r[0].dirty = 1;
+       r[1].dirty = 1;
 
        return ERROR_OK;
 }
@@ -258,8 +259,9 @@ int arm920t_write_cp15_interpreted(struct target *target,
                uint32_t cp15_opcode, uint32_t value, uint32_t address)
 {
        uint32_t cp15c15 = 0x0;
-       struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_armv4_5(target);
        uint32_t regs[2];
+       struct reg *r = armv4_5->core_cache->reg_list;
 
        /* load value, address into R0, R1 */
        regs[0] = value;
@@ -287,8 +289,8 @@ int arm920t_write_cp15_interpreted(struct target *target,
        if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
 
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
+       r[0].dirty = 1;
+       r[1].dirty = 1;
 
        return ERROR_OK;
 }
@@ -436,7 +438,7 @@ int arm920t_arch_state(struct target *target)
        };
 
        struct arm920t_common *arm920t = target_to_arm920(target);
-       struct armv4_5_common_s *armv4_5;
+       struct arm *armv4_5;
 
        if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
        {
@@ -555,7 +557,7 @@ int arm920t_soft_reset_halt(struct target *target)
        int retval = ERROR_OK;
        struct arm920t_common *arm920t = target_to_arm920(target);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+       struct arm *armv4_5 = &arm7_9->armv4_5_common;
        struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        if ((retval = target_halt(target)) != ERROR_OK)
@@ -668,7 +670,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        struct target *target = get_current_target(CMD_CTX);
        struct arm920t_common *arm920t = target_to_arm920(target);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+       struct arm *armv4_5 = &arm7_9->armv4_5_common;
        uint32_t cp15c15;
        uint32_t cp15_ctrl, cp15_ctrl_saved;
        uint32_t regs[16];
@@ -678,6 +680,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        FILE *output;
        struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
        int segment, index;
+       struct reg *r;
 
        retval = arm920t_verify_pointer(CMD_CTX, arm920t);
        if (retval != ERROR_OK)
@@ -893,17 +896,22 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
 
-       /* mark registers dirty. */
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
+       /* force writeback of the valid data */
+       r = armv4_5->core_cache->reg_list;
+       r[0].dirty = r[0].valid;
+       r[1].dirty = r[1].valid;
+       r[2].dirty = r[2].valid;
+       r[3].dirty = r[3].valid;
+       r[4].dirty = r[4].valid;
+       r[5].dirty = r[5].valid;
+       r[6].dirty = r[6].valid;
+       r[7].dirty = r[7].valid;
+
+       r = arm_reg_current(armv4_5, 8);
+       r->dirty = r->valid;
+
+       r = arm_reg_current(armv4_5, 9);
+       r->dirty = r->valid;
 
        return ERROR_OK;
 }
@@ -914,7 +922,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
        struct target *target = get_current_target(CMD_CTX);
        struct arm920t_common *arm920t = target_to_arm920(target);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+       struct arm *armv4_5 = &arm7_9->armv4_5_common;
        uint32_t cp15c15;
        uint32_t cp15_ctrl, cp15_ctrl_saved;
        uint32_t regs[16];
@@ -924,6 +932,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
        uint32_t Dlockdown, Ilockdown;
        struct arm920t_tlb_entry d_tlb[64], i_tlb[64];
        int victim;
+       struct reg *r;
 
        retval = arm920t_verify_pointer(CMD_CTX, arm920t);
        if (retval != ERROR_OK)
@@ -1176,17 +1185,22 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
        if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
 
-       /* mark registers dirty */
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
+       /* force writeback of the valid data */
+       r = armv4_5->core_cache->reg_list;
+       r[0].dirty = r[0].valid;
+       r[1].dirty = r[1].valid;
+       r[2].dirty = r[2].valid;
+       r[3].dirty = r[3].valid;
+       r[4].dirty = r[4].valid;
+       r[5].dirty = r[5].valid;
+       r[6].dirty = r[6].valid;
+       r[7].dirty = r[7].valid;
+
+       r = arm_reg_current(armv4_5, 8);
+       r->dirty = r->valid;
+
+       r = arm_reg_current(armv4_5, 9);
+       r->dirty = r->valid;
 
        return ERROR_OK;
 }
@@ -1347,36 +1361,56 @@ static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t
        return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
 }
 
+static const struct command_registration arm920t_exec_command_handlers[] = {
+       {
+               .name = "cp15",
+               .handler = &arm920t_handle_cp15_command,
+               .mode = COMMAND_EXEC,
+               .help = "display/modify cp15 register",
+               .usage = "<num> [value]",
+       },
+       {
+               .name = "cp15i",
+               .handler = &arm920t_handle_cp15i_command,
+               .mode = COMMAND_EXEC,
+               .help = "display/modify cp15 (interpreted access)",
+               .usage = "<opcode> [value] [address]",
+       },
+       {
+               .name = "cache_info",
+               .handler = &arm920t_handle_cache_info_command,
+               .mode = COMMAND_EXEC,
+               .help = "display information about target caches",
+       },
+       {
+               .name = "read_cache",
+               .handler = &arm920t_handle_read_cache_command,
+               .mode = COMMAND_EXEC,
+               .help = "display I/D cache content",
+       },
+       {
+               .name = "read_mmu",
+               .handler = &arm920t_handle_read_mmu_command,
+               .mode = COMMAND_EXEC,
+               .help = "display I/D mmu content",
+       },
+       COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration arm920t_command_handlers[] = {
+       {
+               .name = "arm920t",
+               .mode = COMMAND_ANY,
+               .help = "arm920t command group",
+               .chain = arm920t_exec_command_handlers,
+       },
+       COMMAND_REGISTRATION_DONE
+};
+
 /** Registers commands to access coprocessor, cache, and MMU resources. */
 int arm920t_register_commands(struct command_context *cmd_ctx)
 {
-       int retval;
-       struct command *arm920t_cmd;
-
-       retval = arm9tdmi_register_commands(cmd_ctx);
-
-       arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t",
-                       NULL, COMMAND_ANY,
-                       "arm920t specific commands");
-
-       register_command(cmd_ctx, arm920t_cmd, "cp15",
-                       arm920t_handle_cp15_command, COMMAND_EXEC,
-                       "display/modify cp15 register <num> [value]");
-       register_command(cmd_ctx, arm920t_cmd, "cp15i",
-                       arm920t_handle_cp15i_command, COMMAND_EXEC,
-                       "display/modify cp15 (interpreted access) "
-                               "<opcode> [value] [address]");
-       register_command(cmd_ctx, arm920t_cmd, "cache_info",
-                       arm920t_handle_cache_info_command, COMMAND_EXEC,
-                       "display information about target caches");
-       register_command(cmd_ctx, arm920t_cmd, "read_cache",
-                       arm920t_handle_read_cache_command, COMMAND_EXEC,
-                       "display I/D cache content");
-       register_command(cmd_ctx, arm920t_cmd, "read_mmu",
-                       arm920t_handle_read_mmu_command, COMMAND_EXEC,
-                       "display I/D mmu content");
-
-       return retval;
+       arm9tdmi_register_commands(cmd_ctx);
+       return register_commands(cmd_ctx, NULL, arm920t_command_handlers);
 }
 
 /** Holds methods for ARM920 targets. */
Cloned from https://git.code.sf.net/p/openocd/code