Edgar Grimberg sharpened the str912 target script.

[openocd] / src / target / arm920t.c

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 1dae23192e02babf4839a6e432600fe02ec5dda3..2468202fbc03de1893b2035388e717e90751d1d1 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -49,7 +49,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm920t_quit();
-int arm920t_arch_state(struct target_s *target, char *buf, int buf_size);
+int arm920t_arch_state(struct target_s *target);
 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int arm920t_soft_reset_halt(struct target_s *target);
@@ -63,6 +63,8 @@ target_type_t arm920t_target =
        .poll = arm7_9_poll,
        .arch_state = arm920t_arch_state,
 
+       .target_request_data = arm7_9_target_request_data,
+
        .halt = arm7_9_halt,
        .resume = arm7_9_resume,
        .step = arm7_9_step,
@@ -70,13 +72,15 @@ target_type_t arm920t_target =
        .assert_reset = arm7_9_assert_reset,
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm920t_soft_reset_halt,
+       .prepare_reset_halt = arm7_9_prepare_reset_halt,
        
        .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
        .read_memory = arm920t_read_memory,
        .write_memory = arm920t_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
-
+       .checksum_memory = arm7_9_checksum_memory,
+       
        .run_algorithm = armv4_5_run_algorithm,
 
        .add_breakpoint = arm7_9_add_breakpoint,
@@ -102,7 +106,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
        
        jtag_add_end_state(TAP_RTI);
        arm_jtag_scann(jtag_info, 0xf);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
        fields[0].device = jtag_info->chain_pos;
        fields[0].num_bits = 1;
@@ -153,7 +157,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
        jtag_execute_queue();
-       DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
+       LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
 #endif
 
        return ERROR_OK;
@@ -174,7 +178,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
        
        jtag_add_end_state(TAP_RTI);
        arm_jtag_scann(jtag_info, 0xf);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
        fields[0].device = jtag_info->chain_pos;
        fields[0].num_bits = 1;
@@ -219,7 +223,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
        jtag_add_dr_scan(4, fields, -1);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
-       DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
+       LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
 #endif
 
        return ERROR_OK;
@@ -238,7 +242,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
        
        jtag_add_end_state(TAP_RTI);
        arm_jtag_scann(jtag_info, 0xf);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
        
        buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 
@@ -290,7 +294,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
        
        if (jtag_execute_queue() != ERROR_OK)
        {
-               ERROR("failed executing JTAG queue, exiting");
+               LOG_ERROR("failed executing JTAG queue, exiting");
                exit(-1);
        }
        
@@ -328,7 +332,7 @@ int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address
        jtag_execute_queue();
        
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
-       DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
+       LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
 #endif
 
        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
@@ -363,7 +367,7 @@ int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value,
        arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
-       DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
+       LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
 #endif
 
        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
@@ -434,7 +438,7 @@ void arm920t_post_debug_entry(target_t *target)
        /* examine cp15 control reg */
        arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
        jtag_execute_queue();
-       DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
+       LOG_DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
 
        if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
        {
@@ -455,7 +459,7 @@ void arm920t_post_debug_entry(target_t *target)
        arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
        arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
        
-       DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
+       LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
                arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);  
 
        if (arm920t->preserve_cache)
@@ -532,7 +536,7 @@ int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar
        return ERROR_OK;
 }
 
-int arm920t_arch_state(struct target_s *target, char *buf, int buf_size)
+int arm920t_arch_state(struct target_s *target)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -546,12 +550,11 @@ int arm920t_arch_state(struct target_s *target, char *buf, int buf_size)
        
        if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
        {
-               ERROR("BUG: called for a non-ARMv4/5 target");
+               LOG_ERROR("BUG: called for a non-ARMv4/5 target");
                exit(-1);
        }
        
-       snprintf(buf, buf_size,
-                       "target halted in %s state due to %s, current mode: %s\n"
+       LOG_USER(       "target halted in %s state due to %s, current mode: %s\n"
                        "cpsr: 0x%8.8x pc: 0x%8.8x\n"
                        "MMU: %s, D-Cache: %s, I-Cache: %s",
                         armv4_5_state_strings[armv4_5->core_state],
@@ -590,7 +593,7 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou
        {
                if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
                {
-                       DEBUG("D-Cache enabled, writing through to main memory");
+                       LOG_DEBUG("D-Cache enabled, writing through to main memory");
                        u32 pa, cb, ap;
                        int type, domain;
 
@@ -604,7 +607,7 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou
                
                if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
                {
-                       DEBUG("I-Cache enabled, invalidating affected I-Cache line");
+                       LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
                        arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
                }
        }
@@ -619,16 +622,27 @@ int arm920t_soft_reset_halt(struct target_s *target)
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
        arm920t_common_t *arm920t = arm9tdmi->arch_info;
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       int i;
        
-       if (target->state == TARGET_RUNNING)
+       target->type->halt(target);
+       
+       for (i=0; i<10; i++)
        {
-               target->type->halt(target);
+               if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+               {
+                       embeddedice_read_reg(dbg_stat);
+                       jtag_execute_queue();
+               } else
+               {
+                       break;
+               }
+               /* do not eat all CPU, time out after 1 se*/
+               usleep(100*1000);
        }
-       
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
+       if (i==10)
        {
-               embeddedice_read_reg(dbg_stat);
-               jtag_execute_queue();
+               LOG_ERROR("Failed to halt CPU after 1 sec");
+               return ERROR_TARGET_TIMEOUT;
        }
        
        target->state = TARGET_HALTED;
@@ -711,10 +725,11 @@ int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **
        int chain_pos;
        char *variant = NULL;
        arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t));
+       memset(arm920t, 0, sizeof(*arm920t));
        
        if (argc < 4)
        {
-               ERROR("'target arm920t' requires at least one additional argument");
+               LOG_ERROR("'target arm920t' requires at least one additional argument");
                exit(-1);
        }
        
@@ -723,7 +738,7 @@ int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **
        if (argc >= 5)
                variant = args[4];
        
-       DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
+       LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
        
        arm920t_init_arch_info(target, arm920t, chain_pos, variant);
 
@@ -785,7 +800,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
        
        if ((output = fopen(args[0], "w")) == NULL)
        {
-               DEBUG("error opening cache content file");
+               LOG_DEBUG("error opening cache content file");
                return ERROR_OK;
        }
        
@@ -985,17 +1000,17 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
        
        fclose(output);
        
-       /* mark registers dirty */
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1;
+       /* mark registers dirty. */
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
        
        return ERROR_OK;
 }
@@ -1026,7 +1041,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
        
        if ((output = fopen(args[0], "w")) == NULL)
        {
-               DEBUG("error opening mmu content file");
+               LOG_DEBUG("error opening mmu content file");
                return ERROR_OK;
        }
        
@@ -1247,16 +1262,16 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
        fclose(output);
        
        /* mark registers dirty */
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
        
        return ERROR_OK;
 }