arm: add error propagation for enable/disable mmu caches

[openocd] / src / target / arm920t.c

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index fe2ff015e742df4b37b5c1cc7242d833e810d35c..a80a37810dba79e08b89f9f1e677887a1ba1a070 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -1,3 +1,4 @@
+
 /***************************************************************************
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
@@ -317,7 +318,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
 }
 
 // EXPORTED to FA256
-uint32_t arm920t_get_ttb(struct target *target)
+int arm920t_get_ttb(struct target *target, uint32_t *result)
 {
        int retval;
        uint32_t ttb = 0x0;
@@ -327,18 +328,24 @@ uint32_t arm920t_get_ttb(struct target *target)
                        0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
                return retval;
 
-       return ttb;
+       *result = ttb;
+       return ERROR_OK;
 }
 
 // EXPORTED to FA256
-void arm920t_disable_mmu_caches(struct target *target, int mmu,
+int arm920t_disable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
-       jtag_execute_queue();
+       retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control &= ~0x1U;
@@ -349,18 +356,24 @@ void arm920t_disable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
                cp15_control &= ~0x1000U;
 
-       arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       return retval;
 }
 
 // EXPORTED to FA256
-void arm920t_enable_mmu_caches(struct target *target, int mmu,
+int arm920t_enable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
-       jtag_execute_queue();
+       retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control |= 0x1U;
@@ -371,7 +384,8 @@ void arm920t_enable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
                cp15_control |= 0x1000U;
 
-       arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       return retval;
 }
 
 // EXPORTED to FA256
@@ -508,15 +522,12 @@ static int arm920_mmu(struct target *target, int *enabled)
 static int arm920_virt2phys(struct target *target,
                uint32_t virt, uint32_t *phys)
 {
-       int type;
        uint32_t cb;
-       int domain;
-       uint32_t ap;
        struct arm920t_common *arm920t = target_to_arm920(target);
 
        uint32_t ret;
        int retval = armv4_5_mmu_translate_va(target,
-                       &arm920t->armv4_5_mmu, virt, &type, &cb, &domain, &ap, &ret);
+                       &arm920t->armv4_5_mmu, virt, &cb, &ret);
        if (retval != ERROR_OK)
                return retval;
        *phys = ret;
@@ -579,17 +590,14 @@ int arm920t_write_memory(struct target *target, uint32_t address,
                 * in memory marked read only
                 * by MMU
                 */
-               int type;
                uint32_t cb;
-               int domain;
-               uint32_t ap;
                uint32_t pa;
 
                /*
                 * We need physical address and cb
                 */
                retval = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu,
-                               address, &type, &cb, &domain, &ap, &pa);
+                               address, &cb, &pa);
                if (retval != ERROR_OK)
                        return retval;
 
@@ -847,7 +855,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        int i;
        FILE *output;
        struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
-       int segment, index;
+       int segment, index_t;
        struct reg *r;
 
        retval = arm920t_verify_pointer(CMD_CTX, arm920t);
@@ -916,12 +924,12 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                arm920t_write_cp15_physical(target,
                                CP15PHYS_TESTSTATE, cp15c15);
 
-               for (index = 0; index < 64; index++)
+               for (index_t = 0; index_t < 64; index_t++)
                {
                        /* Ra:
                         * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
                         */
-                       regs[0] = 0x0 | (segment << 5) | (index << 26);
+                       regs[0] = 0x0 | (segment << 5) | (index_t << 26);
                        arm9tdmi_write_core_regs(target, 0x1, regs);
 
                        /* set interpret mode */
@@ -955,18 +963,18 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                                return retval;
                        }
 
-                       d_cache[segment][index].cam = regs[9];
+                       d_cache[segment][index_t].cam = regs[9];
 
                        /* mask LFSR[6] */
                        regs[9] &= 0xfffffffe;
                        fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8"
                                PRIx32 ", content (%s):\n",
-                               segment, index, regs[9],
+                               segment, index_t, regs[9],
                                (regs[9] & 0x10) ? "valid" : "invalid");
 
                        for (i = 1; i < 9; i++)
                        {
-                                d_cache[segment][index].data[i] = regs[i];
+                                d_cache[segment][index_t].data[i] = regs[i];
                                 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
                                                i-1, regs[i]);
                        }
@@ -1024,12 +1032,12 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                arm920t_write_cp15_physical(target,
                                CP15PHYS_TESTSTATE, cp15c15);
 
-               for (index = 0; index < 64; index++)
+               for (index_t = 0; index_t < 64; index_t++)
                {
                        /* Ra:
                         * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
                         */
-                       regs[0] = 0x0 | (segment << 5) | (index << 26);
+                       regs[0] = 0x0 | (segment << 5) | (index_t << 26);
                        arm9tdmi_write_core_regs(target, 0x1, regs);
 
                        /* set interpret mode */
@@ -1063,18 +1071,18 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                                return retval;
                        }
 
-                       i_cache[segment][index].cam = regs[9];
+                       i_cache[segment][index_t].cam = regs[9];
 
                        /* mask LFSR[6] */
                        regs[9] &= 0xfffffffe;
                        fprintf(output, "\nsegment: %i, index: %i, "
                                "CAM: 0x%8.8" PRIx32 ", content (%s):\n",
-                               segment, index, regs[9],
+                               segment, index_t, regs[9],
                                (regs[9] & 0x10) ? "valid" : "invalid");
 
                        for (i = 1; i < 9; i++)
                        {
-                                i_cache[segment][index].data[i] = regs[i];
+                                i_cache[segment][index_t].data[i] = regs[i];
                                 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
                                                i-1, regs[i]);
                        }