Uwe Hermann tightned up comments, etc. to follow OpenOCD policy

[openocd] / src / target / arm920t.c

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 805624eebdbd7a88266853d2189d3eb0915ba304..e9a109a5981e27156b995ab20360d0dfa61bb155 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -49,7 +49,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm920t_quit();
-int arm920t_arch_state(struct target_s *target, char *buf, int buf_size);
+int arm920t_arch_state(struct target_s *target);
 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int arm920t_soft_reset_halt(struct target_s *target);
@@ -63,6 +63,8 @@ target_type_t arm920t_target =
        .poll = arm7_9_poll,
        .arch_state = arm920t_arch_state,
 
+       .target_request_data = arm7_9_target_request_data,
+
        .halt = arm7_9_halt,
        .resume = arm7_9_resume,
        .step = arm7_9_step,
@@ -77,7 +79,8 @@ target_type_t arm920t_target =
        .read_memory = arm920t_read_memory,
        .write_memory = arm920t_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
-
+       .checksum_memory = arm7_9_checksum_memory,
+       
        .run_algorithm = armv4_5_run_algorithm,
 
        .add_breakpoint = arm7_9_add_breakpoint,
@@ -145,12 +148,12 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
        fields[3].in_handler = NULL;
        fields[3].in_handler_priv = NULL;
        
-       jtag_add_dr_scan(4, fields, -1, NULL);
+       jtag_add_dr_scan(4, fields, -1);
 
        fields[1].in_handler_priv = value;
        fields[1].in_handler = arm_jtag_buf_to_u32;
 
-       jtag_add_dr_scan(4, fields, -1, NULL);
+       jtag_add_dr_scan(4, fields, -1);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
        jtag_execute_queue();
@@ -217,7 +220,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
        fields[3].in_handler = NULL;
        fields[3].in_handler_priv = NULL;
        
-       jtag_add_dr_scan(4, fields, -1, NULL);
+       jtag_add_dr_scan(4, fields, -1);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
        DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
@@ -283,7 +286,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
        fields[3].in_handler = NULL;
        fields[3].in_handler_priv = NULL;
 
-       jtag_add_dr_scan(4, fields, -1, NULL);
+       jtag_add_dr_scan(4, fields, -1);
 
        arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
@@ -533,7 +536,7 @@ int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar
        return ERROR_OK;
 }
 
-int arm920t_arch_state(struct target_s *target, char *buf, int buf_size)
+int arm920t_arch_state(struct target_s *target)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -551,8 +554,7 @@ int arm920t_arch_state(struct target_s *target, char *buf, int buf_size)
                exit(-1);
        }
        
-       snprintf(buf, buf_size,
-                       "target halted in %s state due to %s, current mode: %s\n"
+       USER(   "target halted in %s state due to %s, current mode: %s\n"
                        "cpsr: 0x%8.8x pc: 0x%8.8x\n"
                        "MMU: %s, D-Cache: %s, I-Cache: %s",
                         armv4_5_state_strings[armv4_5->core_state],
@@ -626,7 +628,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
                target->type->halt(target);
        }
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
+       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
        {
                embeddedice_read_reg(dbg_stat);
                jtag_execute_queue();
@@ -986,17 +988,17 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
        
        fclose(output);
        
-       /* mark registers dirty */
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1;
+       /* mark registers dirty. */
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
        
        return ERROR_OK;
 }
@@ -1248,16 +1250,16 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
        fclose(output);
        
        /* mark registers dirty */
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
        
        return ERROR_OK;
 }