+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
static int arm920_virt2phys(struct target *target,
uint32_t virt, uint32_t *phys)
{
- int type;
uint32_t cb;
- int domain;
- uint32_t ap;
struct arm920t_common *arm920t = target_to_arm920(target);
- uint32_t ret = armv4_5_mmu_translate_va(target,
- &arm920t->armv4_5_mmu, virt, &type, &cb, &domain, &ap);
- if (type == -1)
- {
- return ret;
- }
+ uint32_t ret;
+ int retval = armv4_5_mmu_translate_va(target,
+ &arm920t->armv4_5_mmu, virt, &cb, &ret);
+ if (retval != ERROR_OK)
+ return retval;
*phys = ret;
return ERROR_OK;
}
/* FIX!!!! this should be cleaned up and made much more general. The
* plan is to write up and test on arm920t specifically and
- * then generalize and clean up afterwards. */
+ * then generalize and clean up afterwards.
+ *
+ * Also it should be moved to the callbacks that handle breakpoints
+ * specifically and not the generic memory write fn's. See XScale code.
+ */
if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) &&
((size==2) || (size==4)))
{
* in memory marked read only
* by MMU
*/
- int type;
uint32_t cb;
- int domain;
- uint32_t ap;
uint32_t pa;
/*
* We need physical address and cb
*/
- pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu,
- address, &type, &cb, &domain, &ap);
- if (type == -1)
- return pa;
+ retval = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu,
+ address, &cb, &pa);
+ if (retval != ERROR_OK)
+ return retval;
if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
}
}
- return retval;
+ return ERROR_OK;
}
// EXPORTED to FA256
uint32_t CRn, uint32_t CRm,
uint32_t value);
-int arm920t_init_arch_info(struct target *target,
+static int arm920t_init_arch_info(struct target *target,
struct arm920t_common *arm920t, struct jtag_tap *tap)
{
struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
int i;
FILE *output;
struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
- int segment, index;
+ int segment, index_t;
struct reg *r;
retval = arm920t_verify_pointer(CMD_CTX, arm920t);
arm920t_write_cp15_physical(target,
CP15PHYS_TESTSTATE, cp15c15);
- for (index = 0; index < 64; index++)
+ for (index_t = 0; index_t < 64; index_t++)
{
/* Ra:
* r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
*/
- regs[0] = 0x0 | (segment << 5) | (index << 26);
+ regs[0] = 0x0 | (segment << 5) | (index_t << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
return retval;
}
- d_cache[segment][index].cam = regs[9];
+ d_cache[segment][index_t].cam = regs[9];
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8"
PRIx32 ", content (%s):\n",
- segment, index, regs[9],
+ segment, index_t, regs[9],
(regs[9] & 0x10) ? "valid" : "invalid");
for (i = 1; i < 9; i++)
{
- d_cache[segment][index].data[i] = regs[i];
+ d_cache[segment][index_t].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
i-1, regs[i]);
}
arm920t_write_cp15_physical(target,
CP15PHYS_TESTSTATE, cp15c15);
- for (index = 0; index < 64; index++)
+ for (index_t = 0; index_t < 64; index_t++)
{
/* Ra:
* r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
*/
- regs[0] = 0x0 | (segment << 5) | (index << 26);
+ regs[0] = 0x0 | (segment << 5) | (index_t << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
return retval;
}
- i_cache[segment][index].cam = regs[9];
+ i_cache[segment][index_t].cam = regs[9];
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, "
"CAM: 0x%8.8" PRIx32 ", content (%s):\n",
- segment, index, regs[9],
+ segment, index_t, regs[9],
(regs[9] & 0x10) ? "valid" : "invalid");
for (i = 1; i < 9; i++)
{
- i_cache[segment][index].data[i] = regs[i];
+ i_cache[segment][index_t].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
i-1, regs[i]);
}