cortex a8: add missing error handling for mem_ap_atomic_write_u32()

[openocd] / src / target / arm920t.h

diff --git a/src/target/arm920t.h b/src/target/arm920t.h
index 9a837b52852e82409bf1d9b4aad0279af383fb95..a75f01ab16805e4f36687e61fa46e2957eaaa57c 100644 (file)
--- a/src/target/arm920t.h
+++ b/src/target/arm920t.h
@@ -27,9 +27,9 @@
 
 struct arm920t_common
 {
-       arm9tdmi_common_t arm9tdmi_common;
+       struct arm7_9_common arm7_9_common;
        uint32_t common_magic;
-       armv4_5_mmu_common_t armv4_5_mmu;
+       struct armv4_5_mmu_common armv4_5_mmu;
        uint32_t cp15_control_reg;
        uint32_t d_fsr;
        uint32_t i_fsr;
@@ -39,10 +39,10 @@ struct arm920t_common
 };
 
 static inline struct arm920t_common *
-target_to_arm920(struct target_s *target)
+target_to_arm920(struct target *target)
 {
        return container_of(target->arch_info, struct arm920t_common,
-                       arm9tdmi_common.arm7_9_common.armv4_5_common);
+                       arm7_9_common.armv4_5_common);
 }
 
 struct arm920t_cache_line
@@ -51,26 +51,27 @@ struct arm920t_cache_line
        uint32_t data[8];
 };
 
-typedef struct arm920t_tlb_entry_s
+struct arm920t_tlb_entry
 {
        uint32_t cam;
        uint32_t ram1;
        uint32_t ram2;
-} arm920t_tlb_entry_t;
+};
 
-int arm920t_arch_state(struct target_s *target);
-int arm920t_soft_reset_halt(struct target_s *target);
-int arm920t_read_memory(struct target_s *target,
+int arm920t_arch_state(struct target *target);
+int arm920t_soft_reset_halt(struct target *target);
+int arm920t_read_memory(struct target *target,
        uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int arm920t_write_memory(struct target_s *target,
+int arm920t_write_memory(struct target *target,
        uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-void arm920t_post_debug_entry(target_t *target);
-void arm920t_pre_restore_context(target_t *target);
-       uint32_t arm920t_get_ttb(target_t *target);
-void arm920t_disable_mmu_caches(target_t *target,
+void arm920t_post_debug_entry(struct target *target);
+void arm920t_pre_restore_context(struct target *target);
+       uint32_t arm920t_get_ttb(struct target *target);
+void arm920t_disable_mmu_caches(struct target *target,
        int mmu, int d_u_cache, int i_cache);
-void arm920t_enable_mmu_caches(target_t *target,
+void arm920t_enable_mmu_caches(struct target *target,
        int mmu, int d_u_cache, int i_cache);
-int arm920t_register_commands(struct command_context_s *cmd_ctx);
+
+extern const struct command_registration arm920t_command_handlers[];
 
 #endif /* ARM920T_H */