]> git.sur5r.net Git - openocd/blobdiff - src/target/arm926ejs.c
- added manpage for OpenOCD (thanks to Uwe Hermann)
[openocd] / src / target / arm926ejs.c
index 4d43c17a90c7005df2a7b42fe03e9e51d7b7c70e..b62bc49399b5d3bf51ac54fb4bd2d6d517a824e0 100644 (file)
@@ -477,7 +477,7 @@ void arm926ejs_pre_restore_context(target_t *target)
        /* read-modify-write CP15 cache debug control register 
         * to reenable I/D-cache linefills and disable WT */
        arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
-       cache_dbg_ctrl |= 0x7;
+       cache_dbg_ctrl &= ~0x7;
        arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
 }
 
@@ -566,7 +566,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
                target->type->halt(target);
        }
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
+       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
        {
                embeddedice_read_reg(dbg_stat);
                jtag_execute_queue();