#endif
#include "arm926ejs.h"
-#include "time_support.h"
+#include <helper/time_support.h>
#include "target_type.h"
#include "register.h"
+#include "arm_opcodes.h"
/*
armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common;
- LOG_USER("target halted in %s state due to %s, current mode: %s\n"
- "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
- "MMU: %s, D-Cache: %s, I-Cache: %s",
- armv4_5_state_strings[armv4_5->core_state],
- Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
- arm_mode_name(armv4_5->core_mode),
- buf_get_u32(armv4_5->cpsr->value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+ arm_arch_state(target);
+ LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
state[arm926ejs->armv4_5_mmu.mmu_enabled],
state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
armv4_5->cpsr->dirty = 1;
/* start fetching from 0x0 */
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
- armv4_5->core_cache->reg_list[15].dirty = 1;
- armv4_5->core_cache->reg_list[15].valid = 1;
+ buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
+ armv4_5->pc->dirty = 1;
+ armv4_5->pc->valid = 1;
arm926ejs_disable_mmu_caches(target, 1, 1, 1);
arm926ejs->armv4_5_mmu.mmu_enabled = 0;
{
struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common;
+ arm7_9->armv4_5_common.mrc = arm926ejs_mrc;
+ arm7_9->armv4_5_common.mcr = arm926ejs_mcr;
+
/* initialize arm7/arm9 specific info (including armv4_5) */
arm9tdmi_init_arch_info(target, arm7_9, tap);
return ERROR_OK;
}
-/** Registers commands to access coprocessor, cache, and debug resources. */
-int arm926ejs_register_commands(struct command_context *cmd_ctx)
-{
- int retval;
- struct command *arm926ejs_cmd;
-
- retval = arm9tdmi_register_commands(cmd_ctx);
-
- arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs",
- NULL, COMMAND_ANY,
- "arm926ejs specific commands");
-
- register_command(cmd_ctx, arm926ejs_cmd, "cache_info",
- arm926ejs_handle_cache_info_command, COMMAND_EXEC,
- "display information about target caches");
+static const struct command_registration arm926ejs_exec_command_handlers[] = {
+ {
+ .name = "cache_info",
+ .handler = arm926ejs_handle_cache_info_command,
+ .mode = COMMAND_EXEC,
+ .help = "display information about target caches",
- return retval;
-}
+ },
+ COMMAND_REGISTRATION_DONE
+};
+const struct command_registration arm926ejs_command_handlers[] = {
+ {
+ .chain = arm9tdmi_command_handlers,
+ },
+ {
+ .name = "arm926ejs",
+ .mode = COMMAND_ANY,
+ .help = "arm926ejs command group",
+ .chain = arm926ejs_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
/** Holds methods for ARM926 targets. */
struct target_type arm926ejs_target =
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm926ejs_soft_reset_halt,
- .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+ .get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.write_memory = arm926ejs_write_memory,
.add_watchpoint = arm7_9_add_watchpoint,
.remove_watchpoint = arm7_9_remove_watchpoint,
- .register_commands = arm926ejs_register_commands,
+ .commands = arm926ejs_command_handlers,
.target_create = arm926ejs_target_create,
.init_target = arm9tdmi_init_target,
.examine = arm7_9_examine,
+ .check_reset = arm7_9_check_reset,
.virt2phys = arm926ejs_virt2phys,
.mmu = arm926ejs_mmu,
.read_phys_memory = arm926ejs_read_phys_memory,
.write_phys_memory = arm926ejs_write_phys_memory,
- .mrc = arm926ejs_mrc,
- .mcr = arm926ejs_mcr,
};