- corrected stm32x_handle_options_write_command, incorrect options printed

[openocd] / src / target / arm9tdmi.c

diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 1a53d0d08259a502073c210f7011f3ab8b833d94..3b06b0e48d50155fca4588e86a8eef7ecf062b28 100644 (file)
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -104,7 +104,7 @@ int arm9tdmi_jtag_error_handler(u8 *in_value, void *priv)
        
        DEBUG("caller: %s", caller);
        
-       return ERROR_OK;
+       return ERROR_JTAG_QUEUE_FAILED;
 }
 
 int arm9tdmi_examine_debug_reason(target_t *target)
@@ -117,7 +117,6 @@ int arm9tdmi_examine_debug_reason(target_t *target)
        if ((target->debug_reason != DBG_REASON_DBGRQ)
                        && (target->debug_reason != DBG_REASON_SINGLESTEP))
        {
-               error_handler_t error_handler;
                scan_field_t fields[3];
                u8 databus[4];
                u8 instructionbus[4];
@@ -156,9 +155,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
                fields[2].in_handler_priv = NULL;
                
                arm_jtag_scann(&arm7_9->jtag_info, 0x1);
-               error_handler.error_handler = arm9tdmi_jtag_error_handler;
-               error_handler.error_handler_priv = "arm9tdmi_examine_debug_reason";
-               arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, &error_handler);
+               arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 
                jtag_add_dr_scan(3, fields, TAP_PD, NULL);
                jtag_execute_queue();
@@ -187,7 +184,6 @@ int arm9tdmi_examine_debug_reason(target_t *target)
 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
 {
-       error_handler_t error_handler;
        scan_field_t fields[3];
        u8 out_buf[4];
        u8 instr_buf[4];
@@ -204,10 +200,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
        jtag_add_end_state(TAP_PD);
        arm_jtag_scann(jtag_info, 0x1);
        
-       error_handler.error_handler = arm9tdmi_jtag_error_handler;
-       error_handler.error_handler_priv = "arm9tdmi_clock_out";
-       
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
                
        fields[0].device = jtag_info->chain_pos;
        fields[0].num_bits = 32;
@@ -271,15 +264,11 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 {
        scan_field_t fields[3];
-       error_handler_t error_handler;
 
        jtag_add_end_state(TAP_PD);
        arm_jtag_scann(jtag_info, 0x1);
        
-       error_handler.error_handler = arm9tdmi_jtag_error_handler;
-       error_handler.error_handler_priv = "arm9tdmi_clock_data_in_endianness";
-       
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
                
        fields[0].device = jtag_info->chain_pos;
        fields[0].num_bits = 32;
@@ -340,15 +329,11 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 {
        scan_field_t fields[3];
-       error_handler_t error_handler;
        
        jtag_add_end_state(TAP_PD);
        arm_jtag_scann(jtag_info, 0x1);
        
-       error_handler.error_handler = arm9tdmi_jtag_error_handler;
-       error_handler.error_handler_priv = "arm9tdmi_clock_data_in_endianness";
-       
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
                
        fields[0].device = jtag_info->chain_pos;
        fields[0].num_bits = 32;
@@ -874,16 +859,10 @@ void arm9tdmi_build_reg_cache(target_t *target)
        (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
        arm7_9->eice_cache = (*cache_p)->next;
 
-       if (arm7_9->has_etm)
-       {
-               (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, 0);
-               arm7_9->etm_cache = (*cache_p)->next->next;
-       }
-       
-       if (arm7_9->etb)
+       if (arm7_9->etm_ctx)
        {
-               (*cache_p)->next->next->next = etb_build_reg_cache(arm7_9->etb);
-               arm7_9->etb->reg_cache = (*cache_p)->next->next->next;
+               (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
+               arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next;
        }
 }
 
@@ -947,8 +926,8 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int c
        arm7_9->post_restore_context = NULL;
 
        /* initialize arch-specific breakpoint handling */
-       buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
-       buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
+       arm7_9->arm_bkpt = 0xdeeedeee;
+       arm7_9->thumb_bkpt = 0xdeee;
        
        arm7_9->sw_bkpts_use_wp = 1;
        arm7_9->sw_bkpts_enabled = 0;