#include "target_type.h"
+/*
+ * NOTE: this holds code that's used with multiple ARM9 processors:
+ * - ARM9TDMI (ARMv4T) ... in ARM920, ARM922, and ARM940 cores
+ * - ARM9E-S (ARMv5TE) ... in ARM946, ARM966, and ARM968 cores
+ * - ARM9EJS (ARMv5TEJ) ... in ARM926 core
+ *
+ * In short, the file name is a misnomer ... it is NOT specific to
+ * that first generation ARM9 processor, or cores using it.
+ */
+
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-/* cli handling */
-int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-
/* forward declarations */
-int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp );
-
-int arm9tdmi_quit(void);
+static int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp);
+static int arm9tdmi_quit(void);
target_type_t arm9tdmi_target =
{
.quit = arm9tdmi_quit
};
-arm9tdmi_vector_t arm9tdmi_vectors[] =
+static arm9tdmi_vector_t arm9tdmi_vectors[] =
{
{"reset", ARM9TDMI_RESET_VECTOR},
{"undef", ARM9TDMI_UNDEF_VECTOR},
{"swi", ARM9TDMI_SWI_VECTOR},
{"pabt", ARM9TDMI_PABT_VECTOR},
{"dabt", ARM9TDMI_DABT_VECTOR},
- {"reserved", ARM9TDMI_RESERVED_VECTOR},
{"irq", ARM9TDMI_IRQ_VECTOR},
{"fiq", ARM9TDMI_FIQ_VECTOR},
{0, 0},
}
/* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
-int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
+int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed)
{
int retval = ERROR_OK;
scan_field_t fields[3];
if (in)
{
- fields[0].in_value=(uint8_t *)in;
+ fields[0].in_value = (uint8_t *)in;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
- jtag_add_callback(arm_le_to_h_u32, (uint8_t *)in);
+ jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
}
else
{
}
/* just read data (instruction and data-out = don't care) */
-int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
+int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in)
{
int retval = ERROR_OK;;
scan_field_t fields[3];
jtag_add_dr_scan(3, fields, jtag_get_end_state());
- jtag_add_callback(arm_le_to_h_u32, (uint8_t *)in);
+ jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
jtag_add_runtest(0, jtag_get_end_state());
extern void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
-static int arm9endianness(uint8_t *in, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
+static int arm9endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
{
+ uint8_t *in = (uint8_t *)arg;
arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 0);
return ERROR_OK;
}
/* clock the target, and read the databus
* the *in pointer points to a buffer where elements of 'size' bytes
- * are stored in big (be==1) or little (be==0) endianness
+ * are stored in big (be == 1) or little (be == 0) endianness
*/
int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
{
jtag_add_dr_scan(3, fields, jtag_get_end_state());
- jtag_add_callback4(arm9endianness, in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[0].in_value);
+ jtag_add_callback4(arm9endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[0].in_value);
jtag_add_runtest(0, jtag_get_end_state());
if (in)
{
- LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
+ LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in);
}
else
{
return ERROR_OK;
}
-void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
+static void arm9tdmi_change_to_arm(target_t *target,
+ uint32_t *r0, uint32_t *pc)
{
int retval = ERROR_OK;
/* get pointers to arch-specific information */
*pc -= 0xc;
}
-void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
+void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
{
int i;
/* get pointers to arch-specific information */
}
}
-void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
+static void arm9tdmi_read_core_regs_target_buffer(target_t *target,
+ uint32_t mask, void* buffer, int size)
{
int i;
/* get pointers to arch-specific information */
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
- u32 *buf_u32 = buffer;
- u16 *buf_u16 = buffer;
+ uint32_t *buf_u32 = buffer;
+ uint16_t *buf_u16 = buffer;
uint8_t *buf_u8 = buffer;
/* STMIA r0-15, [r0] at debug speed
}
}
-void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
+static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
}
-void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
+static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
- LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
+ LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
/* MSR1 fetched */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void arm9tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
+static void arm9tdmi_write_xpsr_im8(target_t *target,
+ uint8_t xpsr_im, int rot, int spsr)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
}
}
-void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
+void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
{
int i;
/* get pointers to arch-specific information */
for (i = 0; i <= 15; i++)
{
if (mask & (1 << i))
- /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
+ /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
}
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void arm9tdmi_load_word_regs(target_t *target, u32 mask)
+void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_store_word_regs(target_t *target, u32 mask)
+void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_write_pc(target_t *target, u32 pc)
+static void arm9tdmi_write_pc(target_t *target, uint32_t pc)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_branch_resume_thumb(target_t *target)
+static void arm9tdmi_branch_resume_thumb(target_t *target)
{
LOG_DEBUG("-");
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
}
-void arm9tdmi_enable_single_step(target_t *target, u32 next_pc)
+void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
}
}
-void arm9tdmi_build_reg_cache(target_t *target)
+static void arm9tdmi_build_reg_cache(target_t *target)
{
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
/* get pointers to arch-specific information */
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
reg_cache_t *t;
/* one extra register (vector catch) */
- t=embeddedice_build_reg_cache(target, arm7_9);
- if (t==NULL)
+ t = embeddedice_build_reg_cache(target, arm7_9);
+ if (t == NULL)
return ERROR_FAIL;
(*cache_p) = t;
arm7_9->eice_cache = (*cache_p);
}
target_set_examined(target);
}
- if ((retval=embeddedice_setup(target))!=ERROR_OK)
+ if ((retval = embeddedice_setup(target)) != ERROR_OK)
return retval;
- if ((retval=arm7_9_setup(target))!=ERROR_OK)
+ if ((retval = arm7_9_setup(target)) != ERROR_OK)
return retval;
if (arm7_9->etm_ctx)
{
- if ((retval=etm_setup(target))!=ERROR_OK)
+ if ((retval = etm_setup(target)) != ERROR_OK)
return retval;
}
return ERROR_OK;
return ERROR_OK;
}
-int arm9tdmi_quit(void)
+static int arm9tdmi_quit(void)
{
return ERROR_OK;
}
return ERROR_OK;
}
-int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
+static int arm9tdmi_get_arch_pointers(target_t *target,
+ armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p,
+ arm9tdmi_common_t **arm9tdmi_p)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9;
return ERROR_OK;
}
-int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
{
arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
arm9tdmi_init_arch_info(target, arm9tdmi, target->tap);
+ arm9tdmi->arm7_9_common.armv4_5_common.is_armv4 = true;
return ERROR_OK;
}
-int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
-{
- int retval;
- command_t *arm9tdmi_cmd;
-
- retval = arm7_9_register_commands(cmd_ctx);
- arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
- register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
-
- return retval;
-}
-
-int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_arm9tdmi_catch_vectors_command(
+ struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
arm9tdmi_common_t *arm9tdmi;
reg_t *vector_catch;
- u32 vector_catch_value;
+ uint32_t vector_catch_value;
int i, j;
if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
{
- command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
+ command_print(cmd_ctx, "current target isn't an ARM9 based target");
return ERROR_OK;
}
embeddedice_read_reg(vector_catch);
/* get the current setting */
- vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
+ vector_catch_value = buf_get_u32(vector_catch->value, 0, 8);
if (argc > 0)
{
command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
/* reread current setting */
- vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
+ vector_catch_value = buf_get_u32(
+ vector_catch->value,
+ 0, 8);
break;
}
}
/* store new settings */
- buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
+ buf_set_u32(vector_catch->value, 0, 8, vector_catch_value);
embeddedice_store_reg(vector_catch);
}
return ERROR_OK;
}
+
+int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
+{
+ int retval;
+ command_t *arm9tdmi_cmd;
+
+ retval = arm7_9_register_commands(cmd_ctx);
+ arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9",
+ NULL, COMMAND_ANY,
+ "arm9 specific commands");
+ register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch",
+ handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC,
+ "arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|irq|fiq] ...");
+
+ return retval;
+}
+
projects / openocd / blobdiff