* Copyright (C) 2009 by Oyvind Harboe *
* oyvind.harboe@zylin.com *
* *
+ * Copyright (C) 2009-2010 by David Brownell *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* *
***************************************************************************/
-/* Scan out and in from target ordered uint8_t buffers */
+/**
+ * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
+ * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
+ * discusses operations which access these registers.
+ *
+ * Note that only one scan is performed. If RnW is set, a separate scan
+ * will be needed to collect the data which was read; the "invalue" collects
+ * the posted result of a preceding operation, not the current one.
+ *
+ * @param swjdp the DAP
+ * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
+ * @param reg_addr two significant bits; A[3:2]; for APACC access, the
+ * SELECT register has more addressing bits.
+ * @param RnW false iff outvalue will be written to the DP or AP
+ * @param outvalue points to a 32-bit (little-endian) integer
+ * @param invalue NULL, or points to a 32-bit (little-endian) integer
+ * @param ack points to where the three bit JTAG_ACK_* code will be stored
+ */
static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
arm_jtag_set_instr(jtag_info, instr, NULL);
/* Add specified number of tck clocks before accessing memory bus */
+
+ /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
+ * they provide more time for the (MEM) AP to complete the read ...
+ * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
+ */
if ((instr == JTAG_DP_APACC)
&& ((reg_addr == AP_REG_DRW)
|| ((reg_addr & 0xF0) == AP_REG_BD0))
&& (swjdp->memaccess_tck != 0))
jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
+ /* Scan out a read or write operation using some DP or AP register.
+ * For APACC access with any sticky error flag set, this is discarded.
+ */
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 3;
buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
fields[0].out_value = &out_addr_buf;
fields[0].in_value = ack;
+ /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
+ * complete; data we write is discarded, data we read is unpredictable.
+ * When overrun detect is active, STICKYORUN is set.
+ */
+
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = outvalue;
arm_jtag_set_instr(jtag_info, instr, NULL);
/* Add specified number of tck clocks before accessing memory bus */
+
+ /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
+ * they provide more time for the (MEM) AP to complete the read ...
+ */
if ((instr == JTAG_DP_APACC)
&& ((reg_addr == AP_REG_DRW)
|| ((reg_addr & 0xF0) == AP_REG_BD0))
*/
if ((instr == JTAG_DP_APACC)
&& (swjdp->trans_mode == TRANS_MODE_ATOMIC))
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
return ERROR_OK;
}
*/
if ((instr == JTAG_DP_APACC)
&& (swjdp->trans_mode == TRANS_MODE_ATOMIC))
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
return ERROR_OK;
}
-int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
+int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
{
int retval;
uint32_t ctrlstat;
}
else
{
- LOG_WARNING("Invalid ACK "
- "in JTAG-DP transaction");
+ LOG_WARNING("Invalid ACK %#x "
+ "in JTAG-DP transaction",
+ swjdp->ack);
return ERROR_JTAG_DEVICE_ERROR;
}
/* Check for STICKYERR and STICKYORUN */
if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
{
- LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
+ LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
/* Check power to debug regions */
if ((ctrlstat & 0xf0000000) != 0xf0000000)
{
uint32_t mem_ap_csw, mem_ap_tar;
/* Print information about last AHBAP access */
- LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
+ LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32
+ ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32,
+ swjdp->dp_select_value, swjdp->ap_csw_value,
+ swjdp->ap_tar_value);
if (ctrlstat & SSTICKYORUN)
LOG_ERROR("JTAG-DP OVERRUN - "
"check clock or reduce jtag speed");
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
+ LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
+ LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
+ PRIx32, mem_ap_csw, mem_ap_tar);
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
if (csw != swjdp->ap_csw_value)
{
- /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
+ /* LOG_DEBUG("DAP: Set CSW %x",csw); */
dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
swjdp->ap_csw_value = csw;
}
if (tar != swjdp->ap_tar_value)
{
- /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
+ /* LOG_DEBUG("DAP: Set TAR %x",tar); */
dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
swjdp->ap_tar_value = tar;
}
{
mem_ap_read_u32(swjdp, address, value);
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
}
/*****************************************************************************
{
mem_ap_write_u32(swjdp, address, value);
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
}
/*****************************************************************************
dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
}
- if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
{
wcount = wcount - blocksize;
address = address + 4 * blocksize;
if (nbytes < 4)
{
- if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
+ if (mem_ap_write_buf_u16(swjdp, buffer,
+ nbytes, address) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+ LOG_WARNING("Block write error address "
+ "0x%" PRIx32 ", count 0x%x",
+ address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
memcpy(&outvalue, buffer, sizeof(uint32_t));
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+ LOG_WARNING("Block write error address "
+ "0x%" PRIx32 ", count 0x%x",
+ address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
memcpy(&svalue, buffer, sizeof(uint16_t));
uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
count -= 2;
address += 2;
buffer += 2;
{
if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+ LOG_WARNING("Block write error address "
+ "0x%" PRIx32 ", count 0x%x",
+ address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
memcpy(&outvalue, buffer, sizeof(uint32_t));
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+ LOG_WARNING("Block write error address "
+ "0x%" PRIx32 ", count 0x%x",
+ address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
count--;
address++;
buffer++;
adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
DPAP_READ, 0, buffer + 4 * readcount,
&swjdp->ack);
- if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
{
wcount = wcount - blocksize;
address += 4 * blocksize;
do
{
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
{
dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
if (address & 0x1)
{
for (i = 0; i < 2; i++)
do
{
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
{
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
count--;
address++;
* @todo Rename this. We also need an initialization scheme which account
* for SWD transports not just JTAG; that will need to address differences
* in layering. (JTAG is useful without any debug target; but not SWD.)
+ * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
*/
int ahbap_debugport_init(struct swjdp_common *swjdp)
{
/* Check that we have debug power domains activated */
while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
{
- LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
+ LOG_DEBUG("DAP: wait CDBGPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
{
- LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
+ LOG_DEBUG("DAP: wait CSYSPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
- LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
+ LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
+ ", Debug ROM Address 0x%" PRIx32,
+ swjdp->apsel, idreg, romaddr);
return ERROR_OK;
}
&& ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
}
-int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
+int dap_info_command(struct command_context *cmd_ctx,
+ struct swjdp_common *swjdp, int apsel)
{
uint32_t dbgbase, apid;
uint8_t mem_ap;
uint32_t apselold;
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
+
apselold = swjdp->apsel;
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
- swjdp_transaction_endcheck(swjdp);
+ jtagdp_transaction_endcheck(swjdp);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
- swjdp_transaction_endcheck(swjdp);
+ jtagdp_transaction_endcheck(swjdp);
if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
", CID2 0x%2.2" PRIx32
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
if (apselsave != apsel)
dap_ap_select(swjdp, apsel);
+ /* NOTE: assumes we're talking to a MEM-AP, which
+ * has a base address. There are other kinds of AP,
+ * though they're not common for now. This should
+ * use the ID register to verify it's a MEM-AP.
+ */
dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
if (apselsave != apsel)
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
apsel, apid);
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
if (apselsave != apsel)
dap_ap_select(swjdp, apselsave);