* Copyright (C) 2009 by Oyvind Harboe *
* oyvind.harboe@zylin.com *
* *
+ * Copyright (C) 2009-2010 by David Brownell *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
* is used to access memory mapped resources and is called a MEM-AP. Also a
* JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
+ *
+ * @todo Remove modality (queued/nonqueued, via DAP trans_mode) from all
+ * procedure interfaces. Modal programming interfaces are very error prone.
+ * Procedures should be either queued, or synchronous. Otherwise input
+ * and output constraints are context-sensitive, and it's hard to know
+ * what a block of code will do just by reading it.
*/
/*
*/
if ((instr == JTAG_DP_APACC)
&& (swjdp->trans_mode == TRANS_MODE_ATOMIC))
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
return ERROR_OK;
}
*/
if ((instr == JTAG_DP_APACC)
&& (swjdp->trans_mode == TRANS_MODE_ATOMIC))
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
return ERROR_OK;
}
-int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
+int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
{
int retval;
uint32_t ctrlstat;
}
else
{
- LOG_WARNING("Invalid ACK "
- "in JTAG-DP transaction");
+ LOG_WARNING("Invalid ACK %#x "
+ "in JTAG-DP transaction",
+ swjdp->ack);
return ERROR_JTAG_DEVICE_ERROR;
}
}
}
+ /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
+
/* Check for STICKYERR and STICKYORUN */
if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
{
- LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
+ LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
/* Check power to debug regions */
if ((ctrlstat & 0xf0000000) != 0xf0000000)
- {
ahbap_debugport_init(swjdp);
- }
else
{
uint32_t mem_ap_csw, mem_ap_tar;
- /* Print information about last AHBAP access */
- LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
+ /* Maybe print information about last intended
+ * MEM-AP access; but not if autoincrementing.
+ * *Real* CSW and TAR values are always shown.
+ */
+ if (swjdp->ap_tar_value != (uint32_t) -1)
+ LOG_DEBUG("MEM-AP Cached values: "
+ "ap_bank 0x%" PRIx32
+ ", ap_csw 0x%" PRIx32
+ ", ap_tar 0x%" PRIx32,
+ swjdp->dp_select_value,
+ swjdp->ap_csw_value,
+ swjdp->ap_tar_value);
+
if (ctrlstat & SSTICKYORUN)
- LOG_ERROR("JTAG-DP OVERRUN - "
- "check clock or reduce jtag speed");
+ LOG_ERROR("JTAG-DP OVERRUN - check clock, "
+ "memaccess, or reduce jtag speed");
if (ctrlstat & SSTICKYERR)
LOG_ERROR("JTAG-DP STICKY ERROR");
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
+ LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
+ LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
+ PRIx32, mem_ap_csw, mem_ap_tar);
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
reg_addr, DPAP_READ, 0, value);
}
-int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
+/**
+ * Select one of the APs connected to the specified DAP. The
+ * selection is implicitly used with future AP transactions.
+ * This is a NOP if the specified AP is already selected.
+ *
+ * @param swjdp The DAP
+ * @param apsel Number of the AP to (implicitly) use with further
+ * transactions. This normally identifies a MEM-AP.
+ */
+void dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
{
uint32_t select;
select = (apsel << 24) & 0xFF000000;
swjdp->ap_csw_value = -1;
swjdp->ap_tar_value = -1;
}
-
- return ERROR_OK;
}
static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
swjdp->dp_select_value = select;
}
+ /* FIXME return any fault code from write() call */
return ERROR_OK;
}
scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
DPAP_WRITE, out_value_buf, NULL);
+ /* FIXME return fault code from above calls */
return ERROR_OK;
}
-int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
+/**
+ * Write an AP register value.
+ * This is synchronous iff the mode is set to ATOMIC, in which
+ * case any queued transactions are flushed.
+ *
+ * @param swjdp The DAP whose currently selected AP will be written.
+ * @param reg_addr Eight bit AP register address.
+ * @param value Word to be written at reg_addr
+ *
+ * @return In synchronous mode: ERROR_OK for success, and the register holds
+ * the specified value; else a fault code. In asynchronous mode, a status
+ * code reflecting whether the transaction was properly queued.
+ */
+int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
+ uint32_t reg_addr, uint32_t value)
{
uint8_t out_value_buf[4];
scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
DPAP_WRITE, out_value_buf, NULL);
+ /* FIXME return any fault code from above calls */
return ERROR_OK;
}
-int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
+/**
+ * Read an AP register value.
+ * This is synchronous iff the mode is set to ATOMIC, in which
+ * case any queued transactions are flushed.
+ *
+ * @param swjdp The DAP whose currently selected AP will be read.
+ * @param reg_addr Eight bit AP register address.
+ * @param value Points to where the 32-bit (little-endian) word will be stored.
+ *
+ * @return In synchronous mode: ERROR_OK for success, and *value holds
+ * the specified value; else a fault code. In asynchronous mode, a status
+ * code reflecting whether the transaction was properly queued.
+ */
+int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
+ uint32_t reg_addr, uint32_t *value)
{
dap_dp_bankselect(swjdp, reg_addr);
scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
DPAP_READ, 0, value);
+ /* FIXME return any fault code from above calls */
return ERROR_OK;
}
-/***************************************************************************
- * *
- * AHB-AP access to memory and system registers on AHB bus *
- * *
-***************************************************************************/
-
+/**
+ * Set up transfer parameters for the currently selected MEM-AP.
+ * This is synchronous iff the mode is set to ATOMIC, in which
+ * case any queued transactions are flushed.
+ *
+ * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
+ * initiate data reads or writes using memory or peripheral addresses.
+ * If the CSW is configured for it, the TAR may be automatically
+ * incremented after each transfer.
+ *
+ * @todo Rename to reflect it being specifically a MEM-AP function.
+ *
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
+ * matches the cached value, the register is not changed.
+ * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
+ * matches the cached address, the register is not changed.
+ *
+ * @return In synchronous mode: ERROR_OK for success, and the AP is set
+ * up as requested else a fault code. In asynchronous mode, a status
+ * code reflecting whether the transaction was properly queued.
+ */
int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
{
csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
if (csw != swjdp->ap_csw_value)
{
- /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
+ /* LOG_DEBUG("DAP: Set CSW %x",csw); */
+ /* FIXME if this call fails, fail this procedure! */
dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
swjdp->ap_csw_value = csw;
}
if (tar != swjdp->ap_tar_value)
{
- /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
+ /* LOG_DEBUG("DAP: Set TAR %x",tar); */
+ /* FIXME if this call fails, fail this procedure! */
dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
swjdp->ap_tar_value = tar;
}
+ /* Disable TAR cache when autoincrementing */
if (csw & CSW_ADDRINC_MASK)
- {
- /* Do not cache TAR value when autoincrementing */
swjdp->ap_tar_value = -1;
- }
return ERROR_OK;
}
-/*****************************************************************************
-* *
-* mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) *
-* *
-* Read a uint32_t value from memory or system register *
-* Functionally equivalent to target_read_u32(target, address, uint32_t *value), *
-* but with less overhead *
-*****************************************************************************/
-int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
+/**
+ * Asynchronous (queued) read of a word from memory or a system register.
+ *
+ * @param swjdp The DAP connected to the MEM-AP performing the read.
+ * @param address Address of the 32-bit word to read; it must be
+ * readable by the currently selected MEM-AP.
+ * @param value points to where the word will be stored when the
+ * transaction queue is flushed (assuming no errors).
+ *
+ * @return ERROR_OK for success. Otherwise a fault code.
+ */
+int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
+ uint32_t *value)
{
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
+ /* Use banked addressing (REG_BDx) to avoid some link traffic
+ * (updating TAR) when reading several consecutive addresses.
+ */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
+ address & 0xFFFFFFF0);
dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
+ /* FIXME return any fault code from above calls */
return ERROR_OK;
}
-int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
+/**
+ * Synchronous read of a word from memory or a system register.
+ * As a side effect, this flushes any queued transactions.
+ *
+ * @param swjdp The DAP connected to the MEM-AP performing the read.
+ * @param address Address of the 32-bit word to read; it must be
+ * readable by the currently selected MEM-AP.
+ * @param value points to where the result will be stored.
+ *
+ * @return ERROR_OK for success; *value holds the result.
+ * Otherwise a fault code.
+ */
+int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
+ uint32_t *value)
{
mem_ap_read_u32(swjdp, address, value);
+ /* FIXME return any fault code from above call */
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
}
-/*****************************************************************************
-* *
-* mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) *
-* *
-* Write a uint32_t value to memory or memory mapped register *
-* *
-*****************************************************************************/
-int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
+/**
+ * Asynchronous (queued) write of a word to memory or a system register.
+ *
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param address Address to be written; it must be writable by
+ * the currently selected MEM-AP.
+ * @param value Word that will be written to the address when transaction
+ * queue is flushed (assuming no errors).
+ *
+ * @return ERROR_OK for success. Otherwise a fault code.
+ */
+int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
+ uint32_t value)
{
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
+ /* Use banked addressing (REG_BDx) to avoid some link traffic
+ * (updating TAR) when writing several consecutive addresses.
+ */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
+ address & 0xFFFFFFF0);
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
+ /* FIXME return any fault code from above calls */
return ERROR_OK;
}
-int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
+/**
+ * Synchronous write of a word to memory or a system register.
+ * As a side effect, this flushes any queued transactions.
+ *
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param address Address to be written; it must be writable by
+ * the currently selected MEM-AP.
+ * @param value Word that will be written.
+ *
+ * @return ERROR_OK for success; the data was written. Otherwise a fault code.
+ */
+int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
+ uint32_t value)
{
mem_ap_write_u32(swjdp, address, value);
+ /* FIXME return any fault code from above call */
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
}
/*****************************************************************************
dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
}
- if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
{
wcount = wcount - blocksize;
address = address + 4 * blocksize;
if (nbytes < 4)
{
- if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
+ if (mem_ap_write_buf_u16(swjdp, buffer,
+ nbytes, address) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+ LOG_WARNING("Block write error address "
+ "0x%" PRIx32 ", count 0x%x",
+ address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
memcpy(&outvalue, buffer, sizeof(uint32_t));
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+ LOG_WARNING("Block write error address "
+ "0x%" PRIx32 ", count 0x%x",
+ address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
memcpy(&svalue, buffer, sizeof(uint16_t));
uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
count -= 2;
address += 2;
buffer += 2;
{
if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+ LOG_WARNING("Block write error address "
+ "0x%" PRIx32 ", count 0x%x",
+ address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
memcpy(&outvalue, buffer, sizeof(uint32_t));
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+ LOG_WARNING("Block write error address "
+ "0x%" PRIx32 ", count 0x%x",
+ address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
count--;
address++;
buffer++;
adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
DPAP_READ, 0, buffer + 4 * readcount,
&swjdp->ack);
- if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
{
wcount = wcount - blocksize;
address += 4 * blocksize;
do
{
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
{
dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
if (address & 0x1)
{
for (i = 0; i < 2; i++)
do
{
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
{
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
count--;
address++;
}
/**
- * Initialize a DAP.
+ * Initialize a DAP. This sets up the power domains, prepares the DP
+ * for further use, and arranges to use AP #0 for all AP operations
+ * until dap_ap-select() changes that policy.
+ *
+ * @param swjdp The DAP being initialized.
*
* @todo Rename this. We also need an initialization scheme which account
* for SWD transports not just JTAG; that will need to address differences
* in layering. (JTAG is useful without any debug target; but not SWD.)
+ * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
*/
int ahbap_debugport_init(struct swjdp_common *swjdp)
{
/* Check that we have debug power domains activated */
while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
{
- LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
+ LOG_DEBUG("DAP: wait CDBGPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
{
- LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
+ LOG_DEBUG("DAP: wait CSYSPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
- LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
+ LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
+ ", Debug ROM Address 0x%" PRIx32,
+ swjdp->apsel, idreg, romaddr);
return ERROR_OK;
}
&& ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
}
-int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
+int dap_info_command(struct command_context *cmd_ctx,
+ struct swjdp_common *swjdp, int apsel)
{
uint32_t dbgbase, apid;
uint8_t mem_ap;
uint32_t apselold;
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
+
apselold = swjdp->apsel;
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
- swjdp_transaction_endcheck(swjdp);
+ jtagdp_transaction_endcheck(swjdp);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
- swjdp_transaction_endcheck(swjdp);
+ jtagdp_transaction_endcheck(swjdp);
if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
", CID2 0x%2.2" PRIx32
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
if (apselsave != apsel)
dap_ap_select(swjdp, apsel);
+ /* NOTE: assumes we're talking to a MEM-AP, which
+ * has a base address. There are other kinds of AP,
+ * though they're not common for now. This should
+ * use the ID register to verify it's a MEM-AP.
+ */
dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
if (apselsave != apsel)
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
apsel, apid);
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
if (apselsave != apsel)
dap_ap_select(swjdp, apselsave);
projects / openocd / blobdiff