#define JTAG_DP_APACC 0xB
/* three-bit ACK values for SWD access (sent LSB first) */
-#define SWD_ACK_OK 0x4
-#define SWD_ACK_WAIT 0x2
-#define SWD_ACK_FAULT 0x1
+#define SWD_ACK_OK 0x1
+#define SWD_ACK_WAIT 0x2
+#define SWD_ACK_FAULT 0x4
#define DPAP_WRITE 0
#define DPAP_READ 1
+#define BANK_REG(bank, reg) (((bank) << 4) | (reg))
+
/* A[3:0] for DP registers; A[1:0] are always zero.
* - JTAG accesses all of these via JTAG_DP_DPACC, except for
* IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
* - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
*/
-#define DP_IDCODE 0 /* SWD: read */
-#define DP_ABORT 0 /* SWD: write */
-#define DP_CTRL_STAT 0x4 /* r/w */
-#define DP_WCR 0x4 /* SWD: r/w (mux CTRLSEL) */
-#define DP_RESEND 0x8 /* SWD: read */
-#define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */
-#define DP_RDBUFF 0xC /* read-only */
+#define DP_IDCODE BANK_REG(0x0, 0x0) /* SWD: read */
+#define DP_ABORT BANK_REG(0x0, 0x0) /* SWD: write */
+#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */
+#define DP_RESEND BANK_REG(0x0, 0x8) /* SWD: read */
+#define DP_SELECT BANK_REG(0x0, 0x8) /* JTAG: r/w; SWD: write */
+#define DP_RDBUFF BANK_REG(0x0, 0xC) /* read-only */
+#define DP_WCR BANK_REG(0x1, 0x4) /* SWD: r/w */
-#define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8)) /* 1..4 clocks */
-#define WCR_TO_PRESCALE(wcr) (7 & ((wcr))) /* impl defined */
+#define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */
+#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */
/* Fields of the DP's AP ABORT register */
#define DAPABORT (1 << 0)
*/
uint32_t ap_bank_value;
+ /**
+ * Cache for DP_SELECT bits identifying the current four-word DP
+ * register bank. This caches DP register addresss bits 7:4; JTAG
+ * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
+ */
+ uint32_t dp_bank_value;
+
/**
* Cache for (MEM-AP) AP_REG_CSW register value. This is written to
* configure an access mode, such as autoincrementing AP_REG_TAR during
/* information about current pending SWjDP-AHBAP transaction */
uint8_t ack;
+ /**
+ * Holds the pointer to the destination word for the last queued read,
+ * for use with posted AP read sequence optimization.
+ */
+ uint32_t *last_read;
+
/**
* Configures how many extra tck clocks are added after starting a
* MEM-AP access before we try to read its status (and/or result).
/* true if packed transfers are supported by the MEM-AP */
bool packed_transfers;
+
+ /* true if unaligned memory access is not supported by the MEM-AP */
+ bool unaligned_access_bad;
+
+ /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
+ * despite lack of support in the ARMv7 architecture. Memory access through
+ * the AHB-AP has strange byte ordering these processors, and we need to
+ * swizzle appropriately. */
+ bool ti_be_32_quirks;
};
/**
* both JTAG and SWD transports. All submitted transactions are logically
* queued, until the queue is executed by run(). Some implementations might
* execute transactions as soon as they're submitted, but no status is made
- * availablue until run().
+ * available until run().
*/
struct dap_ops {
/** If the DAP transport isn't SWD, it must be JTAG. Upper level
*/
bool is_swd;
- /** Reads the DAP's IDCODe register. */
- int (*queue_idcode_read)(struct adiv5_dap *dap,
- uint8_t *ack, uint32_t *data);
-
/** DP register read. */
int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
uint32_t *data);
/** AP register write. */
int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
uint32_t data);
- /** AP read block. */
- int (*queue_ap_read_block)(struct adiv5_dap *dap, unsigned reg,
- uint32_t blocksize, uint8_t *buffer);
/** AP operation abort. */
int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
AP_TYPE_JTAG_AP = 0x10 /* JTAG-AP - JTAG master for controlling other JTAG devices */
};
-/**
- * Queue an IDCODE register read. This is primarily useful for SWD
- * transports, where it is required as part of link initialization.
- * (For JTAG, this register is read as part of scan chain setup.)
- *
- * @param dap The DAP used for reading.
- * @param ack Pointer to where transaction status will be stored.
- * @param data Pointer saying where to store the IDCODE value.
- *
- * @return ERROR_OK for success, else a fault code.
- */
-static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
- uint8_t *ack, uint32_t *data)
-{
- assert(dap->ops != NULL);
- return dap->ops->queue_idcode_read(dap, ack, data);
-}
-
/**
* Queue a DP register read.
* Note that not all DP registers are readable; also, that JTAG and SWD
return dap->ops->queue_ap_write(dap, reg, data);
}
-/**
- * Queue an AP block read.
- *
- * @param dap The DAP used for reading.
- * @param reg The number of the AP register being read.
- * @param blocksize The number of the AP register being read.
- * @param buffer Pointer saying where to store the data
- * (in host endianness).
- *
- * @return ERROR_OK for success, else a fault code.
- */
-static inline int dap_queue_ap_read_block(struct adiv5_dap *dap,
- unsigned reg, unsigned blocksize, uint8_t *buffer)
-{
- assert(dap->ops != NULL);
- return dap->ops->queue_ap_read_block(dap, reg, blocksize, buffer);
-}
-
/**
* Queue an AP abort operation. The current AP transaction is aborted,
* including any update of the transaction counter. The AP is left in
return dap->ops->run(dap);
}
+static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
+ uint32_t *value)
+{
+ int retval;
+
+ retval = dap_queue_dp_read(dap, reg, value);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return dap_run(dap);
+}
+
+static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
+ uint32_t mask, uint32_t value, int timeout)
+{
+ assert(timeout > 0);
+ assert((value & mask) == value);
+
+ int ret;
+ uint32_t regval;
+ LOG_DEBUG("DAP: poll %x, mask 0x08%" PRIx32 ", value 0x%08" PRIx32,
+ reg, mask, value);
+ do {
+ ret = dap_dp_read_atomic(dap, reg, ®val);
+ if (ret != ERROR_OK)
+ return ret;
+
+ if ((regval & mask) == value)
+ break;
+
+ alive_sleep(10);
+ } while (--timeout);
+
+ if (!timeout) {
+ LOG_DEBUG("DAP: poll %x timeout", reg);
+ return ERROR_FAIL;
+ } else {
+ return ERROR_OK;
+ }
+}
+
/** Accessor for currently selected DAP-AP number (0..255) */
static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
{
int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
uint32_t address, uint32_t value);
-/* MEM-AP memory mapped bus block transfers */
-int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
- uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
- uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
- uint8_t *buffer, int count, uint32_t address, bool addr_incr);
-int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size,
- uint32_t count, uint32_t address, bool addrinc);
-
-int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
- const uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
- const uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
- const uint8_t *buffer, int count, uint32_t address, bool addr_incr);
-int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size,
- uint32_t count, uint32_t address, bool addrinc);
-
-
/* Queued MEM-AP memory mapped single word transfers with selection of ap */
int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
uint32_t address, uint32_t *value);
int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
uint32_t address, uint32_t value);
-/* Non incrementing buffer functions for accessing fifos */
-int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
- uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
- const uint8_t *buffer, int count, uint32_t address);
-
-/* MEM-AP memory mapped bus block transfers with selection of ap */
-int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
- uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
- uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
- uint8_t *buffer, int count, uint32_t address);
-
-int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
- const uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
- const uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
- const uint8_t *buffer, int count, uint32_t address);
+/* Synchronous MEM-AP memory mapped bus block transfers */
+int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size,
+ uint32_t count, uint32_t address, bool addrinc);
+int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size,
+ uint32_t count, uint32_t address, bool addrinc);
+
+/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
+int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
+int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
+ const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
+
+/* Synchronous, non-incrementing buffer functions for accessing fifos, with
+ * selection of ap */
+int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
+int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
+ const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
/* Initialisation of the debug system, power domains and registers */
int ahbap_debugport_init(struct adiv5_dap *swjdp);
projects / openocd / blobdiff