#define AP_REG_IDR 0xFC /* RO: Identification Register */
/* Fields of the MEM-AP's CSW register */
+#define CSW_SIZE_MASK 7
#define CSW_8BIT 0
#define CSW_16BIT 1
#define CSW_32BIT 2
/* true if unaligned memory access is not supported by the MEM-AP */
bool unaligned_access_bad;
+
+ /* true if tar_value is in sync with TAR register */
+ bool tar_valid;
};
int dap_dp_init(struct adiv5_dap *dap);
int mem_ap_init(struct adiv5_ap *ap);
+/* Invalidate cached DP select and cached TAR and CSW of all APs */
+void dap_invalidate_cache(struct adiv5_dap *dap);
+
/* Probe the AP for ROM Table location */
int dap_get_debugbase(struct adiv5_ap *ap,
uint32_t *dbgbase, uint32_t *apid);
extern const struct command_registration dap_command_handlers[];
+struct adiv5_private_config {
+ int ap_num;
+};
+
+extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi);
+
#endif /* OPENOCD_TARGET_ARM_ADI_V5_H */