* except as coprocessor 10/11 operations
* * Most ARM instructions through ARMv6 are decoded, but some
* of the post-ARMv4 opcodes may not be handled yet
+ * CPS, SDIV, UDIV, LDREX*, STREX*, QASX, ...
* * NEON instructions are not understood (ARMv7-A)
*
* - Thumb/Thumb2 decoding
"\t0x%8.8" PRIx32
"\tSRS%s\tSP%s, #%d",
address, opcode,
- mode, wback, opcode & 0x1f);
+ mode, wback,
+ (unsigned)(opcode & 0x1f));
break;
case 0x08100000:
snprintf(instruction->text, 128, "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tRFE%s\tr%d%s",
address, opcode,
- mode, (opcode >> 16) & 0xf, wback);
+ mode,
+ (unsigned)((opcode >> 16) & 0xf), wback);
break;
default:
return evaluate_unknown(opcode, address, instruction);
mnemonic = "MRRC";
}
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, %x, r%i, r%i, c%i",
- address, opcode, mnemonic, COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
+ "\t%s%s%s p%i, %x, r%i, r%i, c%i",
+ address, opcode, mnemonic,
+ ((opcode & 0xf0000000) == 0xf0000000)
+ ? "2" : COND(opcode),
+ COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm);
}
else /* LDC or STC */
{
CRd = (opcode & 0xf000) >> 12;
Rn = (opcode & 0xf0000) >> 16;
- offset = (opcode & 0xff);
+ offset = (opcode & 0xff) << 2;
/* load/store */
if (opcode & 0x00100000)
N = (opcode & 0x00400000) >> 22;
/* addressing modes */
- if ((opcode & 0x01200000) == 0x01000000) /* immediate offset */
- snprintf(addressing_mode, 32, "[r%i, #%s0x%2.2x*4]", Rn, (U) ? "" : "-", offset);
- else if ((opcode & 0x01200000) == 0x01200000) /* immediate pre-indexed */
- snprintf(addressing_mode, 32, "[r%i, #%s0x%2.2x*4]!", Rn, (U) ? "" : "-", offset);
- else if ((opcode & 0x01200000) == 0x00200000) /* immediate post-indexed */
- snprintf(addressing_mode, 32, "[r%i], #%s0x%2.2x*4", Rn, (U) ? "" : "-", offset);
+ if ((opcode & 0x01200000) == 0x01000000) /* offset */
+ snprintf(addressing_mode, 32, "[r%i, #%s%d]",
+ Rn, U ? "" : "-", offset);
+ else if ((opcode & 0x01200000) == 0x01200000) /* pre-indexed */
+ snprintf(addressing_mode, 32, "[r%i, #%s%d]!",
+ Rn, U ? "" : "-", offset);
+ else if ((opcode & 0x01200000) == 0x00200000) /* post-indexed */
+ snprintf(addressing_mode, 32, "[r%i], #%s%d",
+ Rn, U ? "" : "-", offset);
else if ((opcode & 0x01200000) == 0x00000000) /* unindexed */
- snprintf(addressing_mode, 32, "[r%i], #0x%2.2x", Rn, offset);
+ snprintf(addressing_mode, 32, "[r%i], {%d}",
+ Rn, offset >> 2);
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s p%i, c%i, %s",
- address, opcode, mnemonic, ((opcode & 0xf0000000) == 0xf0000000) ? COND(opcode) : "2",
- (N) ? "L" : "",
- cp_num, CRd, addressing_mode);
+ snprintf(instruction->text, 128, "0x%8.8" PRIx32
+ "\t0x%8.8" PRIx32
+ "\t%s%s%s p%i, c%i, %s",
+ address, opcode, mnemonic,
+ ((opcode & 0xf0000000) == 0xf0000000)
+ ? "2" : COND(opcode),
+ (opcode & (1 << 22)) ? "L" : "",
+ cp_num, CRd, addressing_mode);
}
return ERROR_OK;
}
}
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i%s, {%s}%s",
- address, opcode, mnemonic, COND(opcode), addressing_mode,
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
+ "\t%s%s%s r%i%s, {%s}%s",
+ address, opcode,
+ mnemonic, addressing_mode, COND(opcode),
Rn, (W) ? "!" : "", reg_list, (S) ? "^" : "");
return ERROR_OK;
return ERROR_OK;
}
-int arm_evaluate_opcode(uint32_t opcode, uint32_t address, struct arm_instruction *instruction)
+int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
+ struct arm_instruction *instruction)
{
/* clear fields, to avoid confusion */
memset(instruction, 0, sizeof(struct arm_instruction));
}
/* catch opcodes with [27:25] = b110 */
- if ((opcode & 0x0e000000) == 0x0a000000)
+ if ((opcode & 0x0e000000) == 0x0c000000)
{
/* Coprocessor load/store and double register transfers */
return evaluate_ldc_stc_mcrr_mrrc(opcode, address, instruction);
return evaluate_cdp_mcr_mrc(opcode, address, instruction);
}
- LOG_ERROR("should never reach this point");
+ LOG_ERROR("ARM: should never reach this point (opcode=%08x)",
+ (unsigned) opcode);
return -1;
}
}
}
- LOG_ERROR("should never reach this point (opcode=%04x)",opcode);
+ LOG_ERROR("Thumb: should never reach this point (opcode=%04x)", opcode);
return -1;
}
case 0x0c:
/* move constant to top 16 bits of register */
immed |= (opcode >> 4) & 0xf000;
- sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rn, immed, immed);
+ sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rd, immed, immed);
return ERROR_OK;
case 0x10:
case 0x12:
case 6:
sprintf(cp, "SRS%s\tsp%s, #%d", mode,
t ? "!" : "",
- opcode & 0x1f);
+ (unsigned) (opcode & 0x1f));
return ERROR_OK;
case 1:
mode = "DB";
/* FALL THROUGH */
case 7:
sprintf(cp, "RFE%s\tr%d%s", mode,
- (opcode >> 16) & 0xf,
+ (unsigned) ((opcode >> 16) & 0xf),
t ? "!" : "");
return ERROR_OK;
case 2: