arm_adi_v5: Rename TAR and CSW setters and make them AP-specific

[openocd] / src / target / arm_disassembler.h

diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index 774dd2c2f968105f13efa85864815bae8b31aff0..4aee3519dc5d31ceca269783d43b0245870923b1 100644 (file)
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -15,15 +15,13 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
+
 #ifndef ARM_DISASSEMBLER_H
 #define ARM_DISASSEMBLER_H
 
-#include "types.h"
-
-enum arm_instruction_type
-{
+enum arm_instruction_type {
        ARM_UNKNOWN_INSTUCTION,
 
        /* Branch instructions */
@@ -86,9 +84,14 @@ enum arm_instruction_type
        /* Miscellaneous instructions */
        ARM_CLZ,
 
+       /* Exception return instructions */
+       ARM_ERET,
+
        /* Exception generating instructions */
        ARM_BKPT,
        ARM_SWI,
+       ARM_HVC,
+       ARM_SMC,
 
        /* Coprocessor instructions */
        ARM_CDP,
@@ -120,14 +123,12 @@ enum arm_instruction_type
        ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
 };
 
-struct arm_b_bl_bx_blx_instr
-{
+struct arm_b_bl_bx_blx_instr {
        int reg_operand;
        uint32_t target_address;
 };
 
-union arm_shifter_operand
-{
+union arm_shifter_operand {
        struct {
                uint32_t immediate;
        } immediate;
@@ -143,8 +144,7 @@ union arm_shifter_operand
        } register_shift;
 };
 
-struct arm_data_proc_instr
-{
+struct arm_data_proc_instr {
        int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
        uint8_t S;
        uint8_t Rn;
@@ -152,15 +152,13 @@ struct arm_data_proc_instr
        union arm_shifter_operand shifter_operand;
 };
 
-struct arm_load_store_instr
-{
+struct arm_load_store_instr {
        uint8_t Rd;
        uint8_t Rn;
        uint8_t U;
        int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
        int offset_mode; /* 0: immediate, 1: (scaled) register */
-       union
-       {
+       union {
                uint32_t offset;
                struct {
                        uint8_t Rm;
@@ -170,8 +168,7 @@ struct arm_load_store_instr
        } offset;
 };
 
-struct arm_load_store_multiple_instr
-{
+struct arm_load_store_multiple_instr {
        uint8_t Rn;
        uint32_t register_list;
        uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
@@ -179,8 +176,7 @@ struct arm_load_store_multiple_instr
        uint8_t W;
 };
 
-struct arm_instruction
-{
+struct arm_instruction {
        enum arm_instruction_type type;
        char text[128];
        uint32_t opcode;