* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
-#ifndef ARM_DISASSEMBLER_H
-#define ARM_DISASSEMBLER_H
-#include "types.h"
+#ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H
+#define OPENOCD_TARGET_ARM_DISASSEMBLER_H
-enum arm_instruction_type
-{
+enum arm_instruction_type {
ARM_UNKNOWN_INSTUCTION,
/* Branch instructions */
/* Miscellaneous instructions */
ARM_CLZ,
+ /* Exception return instructions */
+ ARM_ERET,
+
/* Exception generating instructions */
ARM_BKPT,
ARM_SWI,
+ ARM_HVC,
+ ARM_SMC,
/* Coprocessor instructions */
ARM_CDP,
ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
};
-struct arm_b_bl_bx_blx_instr
-{
+struct arm_b_bl_bx_blx_instr {
int reg_operand;
uint32_t target_address;
};
-union arm_shifter_operand
-{
+union arm_shifter_operand {
struct {
uint32_t immediate;
} immediate;
} register_shift;
};
-struct arm_data_proc_instr
-{
+struct arm_data_proc_instr {
int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
uint8_t S;
uint8_t Rn;
union arm_shifter_operand shifter_operand;
};
-struct arm_load_store_instr
-{
+struct arm_load_store_instr {
uint8_t Rd;
uint8_t Rn;
uint8_t U;
int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
int offset_mode; /* 0: immediate, 1: (scaled) register */
- union
- {
+ union {
uint32_t offset;
struct {
uint8_t Rm;
} offset;
};
-struct arm_load_store_multiple_instr
-{
+struct arm_load_store_multiple_instr {
uint8_t Rn;
uint32_t register_list;
uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
uint8_t W;
};
-struct arm_instruction
-{
+struct arm_instruction {
enum arm_instruction_type type;
char text[128];
uint32_t opcode;
struct arm_instruction *instruction);
int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
struct arm_instruction *instruction);
-int thumb2_opcode(target_t *target, uint32_t address,
+int thumb2_opcode(struct target *target, uint32_t address,
struct arm_instruction *instruction);
int arm_access_size(struct arm_instruction *instruction);
#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
-#endif /* ARM_DISASSEMBLER_H */
+#endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */