* registers are compatible.
*/
-struct dpm_bp {
- struct breakpoint *bp;
- /* bp->address == breakpoint value register
- * control == breakpoint control register
- */
+struct dpm_bpwp {
+ unsigned number;
+ uint32_t address;
uint32_t control;
/* true if hardware state needs flushing */
bool dirty;
};
+struct dpm_bp {
+ struct breakpoint *bp;
+ struct dpm_bpwp bpwp;
+};
+
struct dpm_wp {
struct watchpoint *wp;
- /* wp->address == watchpoint value register
- * control == watchpoint control register
- */
- uint32_t control;
- /* true if hardware state needs flushing */
- bool dirty;
+ struct dpm_bpwp bpwp;
};
/**
struct dpm_bp *dbp;
struct dpm_wp *dwp;
+ /** Address of the instruction which triggered a watchpoint. */
+ uint32_t wp_pc;
+
+ /** Recent value of DSCR. */
+ uint32_t dscr;
+
// FIXME -- read/write DCSR methods and symbols
};
int arm_dpm_setup(struct arm_dpm *dpm);
-int arm_dpm_reinitialize(struct arm_dpm *dpm);
+int arm_dpm_initialize(struct arm_dpm *dpm);
int arm_dpm_read_current_registers(struct arm_dpm *);
int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
+void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
+
+/* Subset of DSCR bits; see ARMv7a arch spec section C10.3.1.
+ * Not all v7 bits are valid in v6.
+ */
+#define DSCR_CORE_HALTED (1 << 0)
+#define DSCR_CORE_RESTARTED (1 << 1)
+#define DSCR_INT_DIS (1 << 11)
+#define DSCR_ITR_EN (1 << 13)
+#define DSCR_HALT_DBG_MODE (1 << 14)
+#define DSCR_MON_DBG_MODE (1 << 15)
+#define DSCR_INSTR_COMP (1 << 24)
+#define DSCR_DTR_TX_FULL (1 << 29)
+#define DSCR_DTR_RX_FULL (1 << 30)
+
+#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
+
+void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
+
#endif /* __ARM_DPM_H */