arm: add error propagation for enable/disable mmu caches

[openocd] / src / target / arm_simulator.c

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 443f29bf230f4b67e563890dd6914115b9344996..0f6fe3f5e1fb972ce8ffedef969dc6e923ef1ae7 100644 (file)
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -24,6 +24,7 @@
 #include "config.h"
 #endif
 
+#include "arm.h"
 #include "armv4_5.h"
 #include "arm_disassembler.h"
 #include "arm_simulator.h"
@@ -278,7 +279,7 @@ static int thumb_pass_branch_condition(uint32_t cpsr, uint16_t opcode)
  * if the dry_run_pc argument is provided, no state is changed,
  * but the new pc is stored in the variable pointed at by the argument
  */
-int arm_simulate_step_core(struct target *target,
+static int arm_simulate_step_core(struct target *target,
                uint32_t *dry_run_pc, struct arm_sim_interface *sim)
 {
        uint32_t current_pc = sim->get_reg(sim, 15);
@@ -363,42 +364,42 @@ int arm_simulate_step_core(struct target *target,
        /* branch instructions */
        if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX))
        {
-               uint32_t target;
+               uint32_t target_address;
 
                if (instruction.info.b_bl_bx_blx.reg_operand == -1)
                {
-                       target = instruction.info.b_bl_bx_blx.target_address;
+                       target_address = instruction.info.b_bl_bx_blx.target_address;
                }
                else
                {
-                       target = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
+                       target_address = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
                        if (instruction.info.b_bl_bx_blx.reg_operand == 15)
                        {
-                               target += 2 * instruction_size;
+                               target_address += 2 * instruction_size;
                        }
                }
 
                if (dry_run_pc)
                {
-                       *dry_run_pc = target & ~1;
+                       *dry_run_pc = target_address & ~1;
                        return ERROR_OK;
                }
                else
                {
                        if (instruction.type == ARM_B)
                        {
-                               sim->set_reg(sim, 15, target);
+                               sim->set_reg(sim, 15, target_address);
                        }
                        else if (instruction.type == ARM_BL)
                        {
                                uint32_t old_pc = sim->get_reg(sim, 15);
                                int T = (sim->get_state(sim) == ARM_STATE_THUMB);
                                sim->set_reg_mode(sim, 14, old_pc + 4 + T);
-                               sim->set_reg(sim, 15, target);
+                               sim->set_reg(sim, 15, target_address);
                        }
                        else if (instruction.type == ARM_BX)
                        {
-                               if (target & 0x1)
+                               if (target_address & 0x1)
                                {
                                        sim->set_state(sim, ARM_STATE_THUMB);
                                }
@@ -406,7 +407,7 @@ int arm_simulate_step_core(struct target *target,
                                {
                                        sim->set_state(sim, ARM_STATE_ARM);
                                }
-                               sim->set_reg(sim, 15, target & 0xfffffffe);
+                               sim->set_reg(sim, 15, target_address & 0xfffffffe);
                        }
                        else if (instruction.type == ARM_BLX)
                        {
@@ -414,7 +415,7 @@ int arm_simulate_step_core(struct target *target,
                                int T = (sim->get_state(sim) == ARM_STATE_THUMB);
                                sim->set_reg_mode(sim, 14, old_pc + 4 + T);
 
-                               if (target & 0x1)
+                               if (target_address & 0x1)
                                {
                                        sim->set_state(sim, ARM_STATE_THUMB);
                                }
@@ -422,7 +423,7 @@ int arm_simulate_step_core(struct target *target,
                                {
                                        sim->set_state(sim, ARM_STATE_ARM);
                                }
-                               sim->set_reg(sim, 15, target & 0xfffffffe);
+                               sim->set_reg(sim, 15, target_address & 0xfffffffe);
                        }
 
                        return ERROR_OK;