ADIv5 clean up AP selection and register caching

[openocd] / src / target / armv4_5.c

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 1c4923b9d20d5ee88650e519e61008ea81a7e498..a4a15b40df695b4b64767d45d7d38ce207ccced3 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -577,6 +577,7 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
                cache->num_regs++;
        }
 
+       arm->pc = reg_list + 15;
        arm->cpsr = reg_list + ARMV4_5_CPSR;
        arm->core_cache = cache;
        return cache;
@@ -598,8 +599,7 @@ int arm_arch_state(struct target *target)
                        debug_reason_name(target),
                        arm_mode_name(armv4_5->core_mode),
                        buf_get_u32(armv4_5->cpsr->value, 0, 32),
-                       buf_get_u32(armv4_5->core_cache->reg_list[15].value,
-                                       0, 32),
+                       buf_get_u32(armv4_5->pc->value, 0, 32),
                        armv4_5->is_semihosting ? ", semihosting" : "");
 
        return ERROR_OK;
@@ -928,22 +928,22 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 static const struct command_registration arm_exec_command_handlers[] = {
        {
                .name = "reg",
-               .handler = &handle_armv4_5_reg_command,
+               .handler = handle_armv4_5_reg_command,
                .mode = COMMAND_EXEC,
                .help = "display ARM core registers",
        },
        {
                .name = "core_state",
-               .handler = &handle_armv4_5_core_state_command,
+               .handler = handle_armv4_5_core_state_command,
                .mode = COMMAND_EXEC,
-               .usage = "<arm | thumb>",
+               .usage = "['arm'|'thumb']",
                .help = "display/change ARM core state",
        },
        {
                .name = "disassemble",
-               .handler = &handle_armv4_5_disassemble_command,
+               .handler = handle_armv4_5_disassemble_command,
                .mode = COMMAND_EXEC,
-               .usage = "<address> [<count> ['thumb']]",
+               .usage = "address [count ['thumb']]",
                .help = "disassemble instructions ",
        },
        {
@@ -1018,11 +1018,10 @@ static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit
        }
 
        /* fast exit: ARMv5+ code can use BKPT */
-       if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value,
-                               0, 32) != exit_point)
+       if (exit_point && buf_get_u32(armv4_5->pc->value, 0, 32) != exit_point)
        {
                LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
-                       buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+                       buf_get_u32(armv4_5->pc->value, 0, 32));
                return ERROR_TARGET_TIMEOUT;
        }
 
@@ -1426,10 +1425,12 @@ int arm_init_arch_info(struct target *target, struct arm *armv4_5)
        armv4_5->target = target;
 
        armv4_5->common_magic = ARM_COMMON_MAGIC;
-       arm_set_cpsr(armv4_5, ARM_MODE_USR);
 
        /* core_type may be overridden by subtype logic */
-       armv4_5->core_type = ARM_MODE_ANY;
+       if (armv4_5->core_type != ARM_MODE_THREAD) {
+               armv4_5->core_type = ARM_MODE_ANY;
+               arm_set_cpsr(armv4_5, ARM_MODE_USR);
+       }
 
        /* default full_context() has no core-specific optimizations */
        if (!armv4_5->full_context && armv4_5->read_core_reg)