#include "config.h"
#endif
+#include "arm.h"
#include "armv4_5.h"
#include "arm_jtag.h"
#include "breakpoints.h"
cache->num_regs++;
}
+ arm->pc = reg_list + 15;
arm->cpsr = reg_list + ARMV4_5_CPSR;
arm->core_cache = cache;
return cache;
}
-int armv4_5_arch_state(struct target *target)
+int arm_arch_state(struct target *target)
{
struct arm *armv4_5 = target_to_arm(target);
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
- arm_state_strings[armv4_5->core_state],
- Jim_Nvp_value2name_simple(nvp_target_debug_reason,
- target->debug_reason)->name,
- arm_mode_name(armv4_5->core_mode),
- buf_get_u32(armv4_5->cpsr->value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[15].value,
- 0, 32),
+ arm_state_strings[armv4_5->core_state],
+ debug_reason_name(target),
+ arm_mode_name(armv4_5->core_mode),
+ buf_get_u32(armv4_5->cpsr->value, 0, 32),
+ buf_get_u32(armv4_5->pc->value, 0, 32),
armv4_5->is_semihosting ? ", semihosting" : "");
return ERROR_OK;
static const struct command_registration arm_exec_command_handlers[] = {
{
.name = "reg",
- .handler = &handle_armv4_5_reg_command,
+ .handler = handle_armv4_5_reg_command,
.mode = COMMAND_EXEC,
.help = "display ARM core registers",
},
{
.name = "core_state",
- .handler = &handle_armv4_5_core_state_command,
+ .handler = handle_armv4_5_core_state_command,
.mode = COMMAND_EXEC,
- .usage = "<arm | thumb>",
+ .usage = "['arm'|'thumb']",
.help = "display/change ARM core state",
},
{
.name = "disassemble",
- .handler = &handle_armv4_5_disassemble_command,
+ .handler = handle_armv4_5_disassemble_command,
.mode = COMMAND_EXEC,
- .usage = "<address> [<count> ['thumb']]",
+ .usage = "address [count ['thumb']]",
.help = "disassemble instructions ",
},
{
COMMAND_REGISTRATION_DONE
};
-int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
+int arm_get_gdb_reg_list(struct target *target,
+ struct reg **reg_list[], int *reg_list_size)
{
struct arm *armv4_5 = target_to_arm(target);
int i;
}
/* fast exit: ARMv5+ code can use BKPT */
- if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value,
- 0, 32) != exit_point)
+ if (exit_point && buf_get_u32(armv4_5->pc->value, 0, 32) != exit_point)
{
LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
- buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ buf_get_u32(armv4_5->pc->value, 0, 32));
return ERROR_TARGET_TIMEOUT;
}
return ERROR_FAIL;
}
-int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
+int arm_init_arch_info(struct target *target, struct arm *armv4_5)
{
target->arch_info = armv4_5;
armv4_5->target = target;
armv4_5->common_magic = ARM_COMMON_MAGIC;
- arm_set_cpsr(armv4_5, ARM_MODE_USR);
/* core_type may be overridden by subtype logic */
- armv4_5->core_type = ARM_MODE_ANY;
+ if (armv4_5->core_type != ARM_MODE_THREAD) {
+ armv4_5->core_type = ARM_MODE_ANY;
+ arm_set_cpsr(armv4_5, ARM_MODE_USR);
+ }
/* default full_context() has no core-specific optimizations */
if (!armv4_5->full_context && armv4_5->read_core_reg)