}
}
-const char *arm_state_strings[] =
+static const char *arm_state_strings[] =
{
"ARM", "Thumb", "Jazelle", "ThumbEE",
};
cache->num_regs++;
}
+ arm->pc = reg_list + 15;
arm->cpsr = reg_list + ARMV4_5_CPSR;
arm->core_cache = cache;
return cache;
debug_reason_name(target),
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[15].value,
- 0, 32),
+ buf_get_u32(armv4_5->pc->value, 0, 32),
armv4_5->is_semihosting ? ", semihosting" : "");
return ERROR_OK;
return ERROR_FAIL;
}
+ if (armv4_5->core_type != ARM_MODE_ANY)
+ {
+ command_print(CMD_CTX, "Microcontroller Profile not supported - use standard reg cmd");
+ return ERROR_OK;
+ }
+
if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
return ERROR_FAIL;
}
+ if (armv4_5->core_type == ARM_MODE_THREAD)
+ {
+ /* armv7m not supported */
+ command_print(CMD_CTX, "Unsupported Command");
+ return ERROR_OK;
+ }
+
if (CMD_ARGC > 0)
{
if (strcmp(CMD_ARGV[0], "arm") == 0)
return ERROR_OK;
}
-COMMAND_HANDLER(handle_armv4_5_disassemble_command)
+COMMAND_HANDLER(handle_arm_disassemble_command)
{
int retval = ERROR_OK;
struct target *target = get_current_target(CMD_CTX);
return ERROR_FAIL;
}
+ if (arm->core_type == ARM_MODE_THREAD)
+ {
+ /* armv7m is always thumb mode */
+ thumb = 1;
+ }
+
switch (CMD_ARGC) {
case 3:
if (strcmp(CMD_ARGV[2], "thumb") != 0)
return JIM_OK;
}
+COMMAND_HANDLER(handle_arm_semihosting_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm *arm = target ? target_to_arm(target) : NULL;
+
+ if (!is_arm(arm)) {
+ command_print(CMD_CTX, "current target isn't an ARM");
+ return ERROR_FAIL;
+ }
+
+ if (!arm->setup_semihosting)
+ {
+ command_print(CMD_CTX, "semihosting not supported for current target");
+ }
+
+ if (CMD_ARGC > 0)
+ {
+ int semihosting;
+
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+
+ if (!target_was_examined(target))
+ {
+ LOG_ERROR("Target not examined yet");
+ return ERROR_FAIL;
+ }
+
+ if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
+ LOG_ERROR("Failed to Configure semihosting");
+ return ERROR_FAIL;
+ }
+
+ /* FIXME never let that "catch" be dropped! */
+ arm->is_semihosting = semihosting;
+ }
+
+ command_print(CMD_CTX, "semihosting is %s",
+ arm->is_semihosting
+ ? "enabled" : "disabled");
+
+ return ERROR_OK;
+}
+
static const struct command_registration arm_exec_command_handlers[] = {
{
.name = "reg",
},
{
.name = "disassemble",
- .handler = handle_armv4_5_disassemble_command,
+ .handler = handle_arm_disassemble_command,
.mode = COMMAND_EXEC,
.usage = "address [count ['thumb']]",
.help = "disassemble instructions ",
.help = "read coprocessor register",
.usage = "cpnum op1 CRn op2 CRm",
},
+ {
+ "semihosting",
+ .handler = handle_arm_semihosting_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable']",
+ .help = "activate support for semihosting operations",
+ },
COMMAND_REGISTRATION_DONE
};
}
/* fast exit: ARMv5+ code can use BKPT */
- if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value,
- 0, 32) != exit_point)
+ if (exit_point && buf_get_u32(armv4_5->pc->value, 0, 32) != exit_point)
{
LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
- buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ buf_get_u32(armv4_5->pc->value, 0, 32));
return ERROR_TARGET_TIMEOUT;
}