cortex_m3: use register_commands()

[openocd] / src / target / armv4_5_cache.h

diff --git a/src/target/armv4_5_cache.h b/src/target/armv4_5_cache.h
index 44bc212e0ab9a00d4ff1b64a48c30d29c624bce9..1a82b671cee2ec435889a85bfeb3401996c0b9ca 100644 (file)
--- a/src/target/armv4_5_cache.h
+++ b/src/target/armv4_5_cache.h
@@ -22,30 +22,33 @@
 
 #include "types.h"
 
-struct command_context_s;
+struct command_context;
 
-typedef struct armv4_5_cachesize_s
+struct armv4_5_cachesize
 {
        int linelen;
        int associativity;
        int nsets;
        int cachesize;
-} armv4_5_cachesize_t;
+};
 
-typedef struct armv4_5_cache_common_s
+struct armv4_5_cache_common
 {
        int ctype;      /* specify supported cache operations */
        int separate;   /* separate caches or unified cache */
-       armv4_5_cachesize_t d_u_size;   /* data cache */
-       armv4_5_cachesize_t i_size; /* instruction cache */
+       struct armv4_5_cachesize d_u_size;      /* data cache */
+       struct armv4_5_cachesize i_size; /* instruction cache */
        int i_cache_enabled;
        int d_u_cache_enabled;
-} armv4_5_cache_common_t;
+};
 
-extern int armv4_5_identify_cache(uint32_t cache_type_reg, armv4_5_cache_common_t *cache);
-extern int armv4_5_cache_state(uint32_t cp15_control_reg, armv4_5_cache_common_t *cache);
+int armv4_5_identify_cache(uint32_t cache_type_reg,
+               struct armv4_5_cache_common *cache);
+int armv4_5_cache_state(uint32_t cp15_control_reg,
+               struct armv4_5_cache_common *cache);
 
-extern int armv4_5_handle_cache_info_command(struct command_context_s *cmd_ctx, armv4_5_cache_common_t *armv4_5_cache);
+int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx,
+               struct armv4_5_cache_common *armv4_5_cache);
 
 enum
 {