armv7m: use consistent arm.cpsr member

[openocd] / src / target / armv7a.c

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 48fdf8b3cde36879caca7b882b488aaecdf9d806..80d7a6e8b64592d4a4a0bad8c63c68a280dea0ca 100644 (file)
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -16,7 +16,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -387,7 +387,7 @@ static int  armv7a_flush_all_data(struct target *target)
                head = target->head;
                while (head != (struct target_list *)NULL) {
                        curr = head->target;
-                       if ((curr->state == TARGET_HALTED)) {
+                       if (curr->state == TARGET_HALTED) {
                                LOG_INFO("Wait flushing data l1 on core %d", curr->coreid);
                                retval = _armv7a_flush_all_data(curr);
                        }
@@ -549,7 +549,7 @@ static int armv7a_read_mpidr(struct target *target)
                armv7a->multi_processor_system = (mpidr >> 30) & 1;
                armv7a->cluster_id = (mpidr >> 8) & 0xf;
                armv7a->cpu_id = mpidr & 0x3;
-               LOG_INFO("%s cluster %x core %x %s", target->cmd_name,
+               LOG_INFO("%s cluster %x core %x %s", target_name(target),
                        armv7a->cluster_id,
                        armv7a->cpu_id,
                        armv7a->multi_processor_system == 0 ? "multi core" : "mono core");
@@ -573,7 +573,8 @@ int armv7a_identify_cache(struct target *target)
        uint32_t cache_selected, clidr;
        uint32_t cache_i_reg, cache_d_reg;
        struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache);
-       armv7a_read_ttbcr(target);
+       if (!armv7a->is_armv7r)
+               armv7a_read_ttbcr(target);
        retval = dpm->prepare(dpm);
 
        if (retval != ERROR_OK)
@@ -747,10 +748,16 @@ int armv7a_arch_state(struct target *target)
 
        arm_arch_state(target);
 
-       LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
-               state[armv7a->armv7a_mmu.mmu_enabled],
-               state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
-               state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
+       if (armv7a->is_armv7r) {
+               LOG_USER("D-Cache: %s, I-Cache: %s",
+                       state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
+                       state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
+       } else {
+               LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
+                       state[armv7a->armv7a_mmu.mmu_enabled],
+                       state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
+                       state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
+       }
 
        if (arm->core_mode == ARM_MODE_ABT)
                armv7a_show_fault_registers(target);