armv7a: cache ttbcr and ttb0/1 on debug state entry

[openocd] / src / target / armv7a.h

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 14112e4ed0267958f2ce392f0044e2dbf83b9078..33f6f5dbea15c75aa23a110e7b9e8d5689db6e7d 100644 (file)
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -87,6 +87,7 @@ struct armv7a_mmu_common {
        /* following field mmu working way */
        int32_t cached;     /* 0: not initialized, 1: initialized */
        uint32_t ttbcr;     /* cache for ttbcr register */
+       uint32_t ttbr[2];
        uint32_t ttbr_mask[2];
        uint32_t ttbr_range[2];