stm32l4x.c: Free r6/7 for 64-bit operations.

[openocd] / src / target / armv7a.h

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index b37b0174bf2e57c3853a8c7651e5ff91c64ef1bc..5ca4eb86ef079390e649f899868e9f2f98cb0567 100644 (file)
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -84,8 +84,6 @@ struct armv7a_cache_common {
        /* outer unified cache if some */
        void *outer_cache;
        int (*flush_all_data_cache)(struct target *target);
-       int (*display_cache_info)(struct command_context *cmd_ctx,
-                       struct armv7a_cache_common *armv7a_cache);
 };
 
 struct armv7a_mmu_common {
@@ -94,7 +92,6 @@ struct armv7a_mmu_common {
        uint32_t ttbcr;     /* cache for ttbcr register */
        uint32_t ttbr_mask[2];
        uint32_t ttbr_range[2];
-       uint32_t os_border;
 
        int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
                        uint32_t count, uint8_t *buffer);
@@ -107,13 +104,11 @@ struct armv7a_common {
        int common_magic;
        struct reg_cache *core_cache;
 
-       struct adiv5_dap dap;
-
        /* Core Debug Unit */
        struct arm_dpm dpm;
        uint32_t debug_base;
-       uint8_t debug_ap;
-       uint8_t memory_ap;
+       struct adiv5_ap *debug_ap;
+       struct adiv5_ap *memory_ap;
        bool memory_ap_available;
        /* mdir */
        uint8_t multi_processor_system;
@@ -174,6 +169,7 @@ target_to_armv7a(struct target *target)
 
 /* See ARMv7a arch spec section C10.7 */
 #define CPUDBG_DSCCR           0x028
+#define CPUDBG_DSMCR           0x02C
 
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS      0xFB8