#define ARMV7A_H
#include "arm_adi_v5.h"
-#include "armv4_5.h"
+#include "arm.h"
#include "armv4_5_mmu.h"
#include "armv4_5_cache.h"
#include "arm_dpm.h"
int common_magic;
struct reg_cache *core_cache;
- /* arm adp debug port */
- struct swjdp_common swjdp_info;
+ struct adiv5_dap dap;
/* Core Debug Unit */
struct arm_dpm dpm;
armv4_5_common);
}
-struct armv7a_algorithm
-{
- int common_magic;
-
- enum armv4_5_mode core_mode;
- enum armv4_5_state core_state;
-};
-
-struct armv7a_core_reg
-{
- int num;
- enum armv4_5_mode mode;
- struct target *target;
- struct armv7a_common *armv7a_common;
-};
+/* register offsets from armv7a.debug_base */
+
+/* See ARMv7a arch spec section C10.2 */
+#define CPUDBG_DIDR 0x000
+
+/* See ARMv7a arch spec section C10.3 */
+#define CPUDBG_WFAR 0x018
+/* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
+#define CPUDBG_DSCR 0x088
+#define CPUDBG_DRCR 0x090
+#define CPUDBG_PRCR 0x310
+#define CPUDBG_PRSR 0x314
+
+/* See ARMv7a arch spec section C10.4 */
+#define CPUDBG_DTRRX 0x080
+#define CPUDBG_ITR 0x084
+#define CPUDBG_DTRTX 0x08c
+
+/* See ARMv7a arch spec section C10.5 */
+#define CPUDBG_BVR_BASE 0x100
+#define CPUDBG_BCR_BASE 0x140
+#define CPUDBG_WVR_BASE 0x180
+#define CPUDBG_WCR_BASE 0x1C0
+#define CPUDBG_VCR 0x01C
+
+/* See ARMv7a arch spec section C10.6 */
+#define CPUDBG_OSLAR 0x300
+#define CPUDBG_OSLSR 0x304
+#define CPUDBG_OSSRR 0x308
+#define CPUDBG_ECR 0x024
+
+/* See ARMv7a arch spec section C10.7 */
+#define CPUDBG_DSCCR 0x028
+
+/* See ARMv7a arch spec section C10.8 */
+#define CPUDBG_AUTHSTATUS 0xFB8
int armv7a_arch_state(struct target *target);
struct reg_cache *armv7a_build_reg_cache(struct target *target,