#ifndef ARMV7A_H
#define ARMV7A_H
-#include <target/arm_adi_v5.h>
-#include <target/armv4_5.h>
+#include "arm_adi_v5.h"
+#include "arm.h"
#include "armv4_5_mmu.h"
#include "armv4_5_cache.h"
-#include <target/arm_dpm.h>
+#include "arm_dpm.h"
enum
{
int common_magic;
struct reg_cache *core_cache;
- /* arm adp debug port */
- struct swjdp_common swjdp_info;
+ struct adiv5_dap dap;
/* Core Debug Unit */
struct arm_dpm dpm;
/* See ARMv7a arch spec section C10.8 */
#define CPUDBG_AUTHSTATUS 0xFB8
-/* DSCR bit numbers (See ARMv7a arch spec section 12.4.5) */
-#define DSCR_CORE_HALTED 0
-#define DSCR_CORE_RESTARTED 1
-#define DSCR_EXT_INT_EN 13
-#define DSCR_HALT_DBG_MODE 14
-#define DSCR_MON_DBG_MODE 15
-#define DSCR_INSTR_COMP 24
-#define DSCR_DTR_TX_FULL 29
-#define DSCR_DTR_RX_FULL 30
-
-struct armv7a_algorithm
-{
- int common_magic;
-
- enum armv4_5_mode core_mode;
- enum armv4_5_state core_state;
-};
-
-struct armv7a_core_reg
-{
- int num;
- enum armv4_5_mode mode;
- struct target *target;
- struct armv7a_common *armv7a_common;
-};
-
int armv7a_arch_state(struct target *target);
struct reg_cache *armv7a_build_reg_cache(struct target *target,
struct armv7a_common *armv7a_common);