avr32: work-in-progress

[openocd] / src / target / armv7m.c

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index f0829c61770e62752d4a59b677ca5533f6f65d13..a73a9bb45b71c0d0207d0120ca88890c60b7c840 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -313,7 +313,7 @@ static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int
        }
 
        armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
-       if (pc != exit_point)
+       if (exit_point && (pc != exit_point))
        {
                LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
                return ERROR_TARGET_TIMEOUT;
@@ -527,7 +527,7 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
        return cache;
 }
 
-int armv7m_setup_semihosting(struct target *target, int enable)
+static int armv7m_setup_semihosting(struct target *target, int enable)
 {
        /* nothing todo for armv7m */
        return ERROR_OK;
@@ -615,8 +615,10 @@ int armv7m_checksum_memory(struct target *target,
        buf_set_u32(reg_params[0].value, 0, 32, address);
        buf_set_u32(reg_params[1].value, 0, 32, count);
 
+       int timeout = 20000 * (1 + (count / (1024 * 1024)));
+
        if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
-               crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
+               crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), timeout, &armv7m_info)) != ERROR_OK)
        {
                LOG_ERROR("error executing cortex_m3 crc algorithm");
                destroy_reg_param(&reg_params[0]);