* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
* *
* ARMv7-M Architecture, Application Level Reference Manual *
* ARM DDI 0405C (September 2008) *
int armv7m_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
+ target_addr_t entry_point, target_addr_t exit_point,
int timeout_ms, void *arch_info)
{
int retval;
int armv7m_start_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
+ target_addr_t entry_point, target_addr_t exit_point,
void *arch_info)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int armv7m_wait_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t exit_point, int timeout_ms,
+ target_addr_t exit_point, int timeout_ms,
void *arch_info)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
armv7m->load_core_reg_u32(target, 15, &pc);
if (exit_point && (pc != exit_point)) {
- LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" PRIx32,
+ LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
pc,
exit_point);
return ERROR_TARGET_TIMEOUT;
struct arm *arm = &armv7m->arm;
uint32_t ctrl, sp;
+ /* avoid filling log waiting for fileio reply */
+ if (arm->semihosting_hit_fileio)
+ return ERROR_OK;
+
ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
LOG_USER("target halted due to %s, current mode: %s %s\n"
- "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
+ "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s",
debug_reason_name(target),
arm_mode_name(arm->core_mode),
armv7m_exception_string(armv7m->exception_number),
buf_get_u32(arm->pc->value, 0, 32),
(ctrl & 0x02) ? 'p' : 'm',
sp,
- arm->is_semihosting ? ", semihosting" : "");
+ arm->is_semihosting ? ", semihosting" : "",
+ arm->is_semihosting_fileio ? " fileio" : "");
return ERROR_OK;
}
return cache;
}
+void armv7m_free_reg_cache(struct target *target)
+{
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct arm *arm = &armv7m->arm;
+ struct reg_cache *cache;
+ struct reg *reg;
+ unsigned int i;
+
+ cache = arm->core_cache;
+
+ if (!cache)
+ return;
+
+ for (i = 0; i < cache->num_regs; i++) {
+ reg = &cache->reg_list[i];
+
+ free(reg->feature);
+ free(reg->reg_data_type);
+ free(reg->value);
+ }
+
+ free(cache->reg_list[0].arch_info);
+ free(cache->reg_list);
+ free(cache);
+
+ arm->core_cache = NULL;
+}
+
static int armv7m_setup_semihosting(struct target *target, int enable)
{
/* nothing todo for armv7m */
/** Generates a CRC32 checksum of a memory region. */
int armv7m_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *checksum)
+ target_addr_t address, uint32_t count, uint32_t *checksum)
{
struct working_area *crc_algorithm;
struct armv7m_algorithm armv7m_info;
struct reg_param reg_params[2];
int retval;
- /* see contrib/loaders/checksum/armv7m_crc.s for src */
-
static const uint8_t cortex_m_crc_code[] = {
- /* main: */
- 0x02, 0x46, /* mov r2, r0 */
- 0x00, 0x20, /* movs r0, #0 */
- 0xC0, 0x43, /* mvns r0, r0 */
- 0x0A, 0x4E, /* ldr r6, CRC32XOR */
- 0x0B, 0x46, /* mov r3, r1 */
- 0x00, 0x24, /* movs r4, #0 */
- 0x0D, 0xE0, /* b ncomp */
- /* nbyte: */
- 0x11, 0x5D, /* ldrb r1, [r2, r4] */
- 0x09, 0x06, /* lsls r1, r1, #24 */
- 0x48, 0x40, /* eors r0, r0, r1 */
- 0x00, 0x25, /* movs r5, #0 */
- /* loop: */
- 0x00, 0x28, /* cmp r0, #0 */
- 0x02, 0xDA, /* bge notset */
- 0x40, 0x00, /* lsls r0, r0, #1 */
- 0x70, 0x40, /* eors r0, r0, r6 */
- 0x00, 0xE0, /* b cont */
- /* notset: */
- 0x40, 0x00, /* lsls r0, r0, #1 */
- /* cont: */
- 0x01, 0x35, /* adds r5, r5, #1 */
- 0x08, 0x2D, /* cmp r5, #8 */
- 0xF6, 0xD1, /* bne loop */
- 0x01, 0x34, /* adds r4, r4, #1 */
- /* ncomp: */
- 0x9C, 0x42, /* cmp r4, r3 */
- 0xEF, 0xD1, /* bne nbyte */
- 0x00, 0xBE, /* bkpt #0 */
- 0xB7, 0x1D, 0xC1, 0x04 /* CRC32XOR: .word 0x04c11db7 */
+#include "../../contrib/loaders/checksum/armv7m_crc.inc"
};
retval = target_alloc_working_area(target, sizeof(cortex_m_crc_code), &crc_algorithm);
return retval;
}
-/** Checks whether a memory region is zeroed. */
+/** Checks whether a memory region is erased. */
int armv7m_blank_check_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *blank)
+ target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value)
{
struct working_area *erase_check_algorithm;
struct reg_param reg_params[3];
struct armv7m_algorithm armv7m_info;
+ const uint8_t *code;
+ uint32_t code_size;
int retval;
- /* see contrib/loaders/erase_check/armv7m_erase_check.s for src */
-
static const uint8_t erase_check_code[] = {
- /* loop: */
- 0x03, 0x78, /* ldrb r3, [r0] */
- 0x01, 0x30, /* adds r0, #1 */
- 0x1A, 0x40, /* ands r2, r2, r3 */
- 0x01, 0x39, /* subs r1, r1, #1 */
- 0xFA, 0xD1, /* bne loop */
- 0x00, 0xBE /* bkpt #0 */
+#include "../../contrib/loaders/erase_check/armv7m_erase_check.inc"
+ };
+ static const uint8_t zero_erase_check_code[] = {
+#include "../../contrib/loaders/erase_check/armv7m_0_erase_check.inc"
};
+ switch (erased_value) {
+ case 0x00:
+ code = zero_erase_check_code;
+ code_size = sizeof(zero_erase_check_code);
+ break;
+ case 0xff:
+ default:
+ code = erase_check_code;
+ code_size = sizeof(erase_check_code);
+ }
+
/* make sure we have a working area */
- if (target_alloc_working_area(target, sizeof(erase_check_code),
+ if (target_alloc_working_area(target, code_size,
&erase_check_algorithm) != ERROR_OK)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
retval = target_write_buffer(target, erase_check_algorithm->address,
- sizeof(erase_check_code), (uint8_t *)erase_check_code);
+ code_size, code);
if (retval != ERROR_OK)
- return retval;
+ goto cleanup;
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARM_MODE_THREAD;
buf_set_u32(reg_params[1].value, 0, 32, count);
init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
- buf_set_u32(reg_params[2].value, 0, 32, 0xff);
+ buf_set_u32(reg_params[2].value, 0, 32, erased_value);
retval = target_run_algorithm(target,
0,
3,
reg_params,
erase_check_algorithm->address,
- erase_check_algorithm->address + (sizeof(erase_check_code) - 2),
+ erase_check_algorithm->address + (code_size - 2),
10000,
&armv7m_info);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
+cleanup:
target_free_working_area(target, erase_check_algorithm);
return retval;
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