/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
+ * *
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
"sp", "lr", "pc",
"xPSR", "msp", "psp",
/* Registers accessed through MSR instructions */
-// "apsr", "iapsr", "ipsr", "epsr",
+ /* "apsr", "iapsr", "ipsr", "epsr", */
"primask", "basepri", "faultmask", "control"
};
"sp", "lr", "pc",
"xPSR", "msp", "psp",
/* Registers accessed through MSR instructions */
-// "dbg_apsr", "iapsr", "ipsr", "epsr",
+ /* "dbg_apsr", "iapsr", "ipsr", "epsr", */
"primask", "basepri", "faultmask", "dbg_control"
};
{18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
/* CORE_SP are accesible using MSR and MRS instructions */
+#if 0
// {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
// {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
// {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
// {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
+#endif
{0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
{0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
if (retval != ERROR_OK)
{
ERROR("JTAG failure");
- armv7m->core_cache->reg_list[num].dirty = 1;
+ armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
return ERROR_JTAG_DEVICE_ERROR;
}
DEBUG("write core reg %i value 0x%x", num , reg_value);
armv7m_common_t *armv7m = target->arch_info;
int i;
- if (target->state != TARGET_HALTED)
- {
- return ERROR_TARGET_NOT_HALTED;
- }
-
*reg_list_size = 26;
*reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
{
if (i < ARMV7NUMCOREREGS)
(*reg_list)[i] = &armv7m->process_context->reg_list[i];
- //(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
+ /* (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; */
else
(*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
}
int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
{
- // get pointers to arch-specific information
+ /* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
enum armv7m_state core_state = armv7m->core_state;
return retval;
}
-int armv7m_arch_state(struct target_s *target, char *buf, int buf_size)
+int armv7m_arch_state(struct target_s *target)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- snprintf(buf, buf_size,
- "target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
+ USER("target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
armv7m_state_strings[armv7m->core_state],
target_debug_reason_strings[target->debug_reason],
armv7m_mode_strings[armv7m->core_mode],
{
return ERROR_OK;
}
+
+int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
+{
+ working_area_t *crc_algorithm;
+ armv7m_algorithm_t armv7m_info;
+ reg_param_t reg_params[2];
+ int retval;
+
+ u16 cortex_m3_crc_code[] = {
+ 0x4602, /* mov r2, r0 */
+ 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
+ 0x460B, /* mov r3, r1 */
+ 0xF04F, 0x0400, /* mov r4, #0 */
+ 0xE013, /* b ncomp */
+ /* nbyte: */
+ 0x5D11, /* ldrb r1, [r2, r4] */
+ 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
+ 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
+
+ 0xF04F, 0x0500, /* mov r5, #0 */
+ /* loop: */
+ 0x2800, /* cmp r0, #0 */
+ 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
+ 0xF105, 0x0501, /* add r5, r5, #1 */
+ 0x4630, /* mov r0, r6 */
+ 0xBFB8, /* it lt */
+ 0xEA86, 0x0007, /* eor r0, r6, r7 */
+ 0x2D08, /* cmp r5, #8 */
+ 0xD1F4, /* bne loop */
+
+ 0xF104, 0x0401, /* add r4, r4, #1 */
+ /* ncomp: */
+ 0x429C, /* cmp r4, r3 */
+ 0xD1E9, /* bne nbyte */
+ /* end: */
+ 0xE7FE, /* b end */
+ 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
+ };
+
+ int i;
+
+ if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
+ {
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ /* convert flash writing code into a buffer in target endianness */
+ for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
+ target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i]);
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARMV7M_MODE_ANY;
+ armv7m_info.core_state = ARMV7M_STATE_THUMB;
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
+
+ buf_set_u32(reg_params[0].value, 0, 32, address);
+ buf_set_u32(reg_params[1].value, 0, 32, count);
+
+ if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
+ crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
+ {
+ ERROR("error executing cortex_m3 crc algorithm");
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ target_free_working_area(target, crc_algorithm);
+ return retval;
+ }
+
+ *checksum = buf_get_u32(reg_params[0].value, 0, 32);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+
+ target_free_working_area(target, crc_algorithm);
+
+ return ERROR_OK;
+}
+
projects / openocd / blobdiff