#ifndef ARMV7M_COMMON_H
#define ARMV7M_COMMON_H
-#include <target/arm_adi_v5.h>
-#include <target/armv4_5.h>
+#include "arm_adi_v5.h"
+#include "arm.h"
/* define for enabling armv7 gdb workarounds */
#if 1
#define ARMV7_GDB_HACKS
#endif
+#ifdef ARMV7_GDB_HACKS
+extern uint8_t armv7m_gdb_dummy_cpsr_value[];
+extern struct reg armv7m_gdb_dummy_cpsr_reg;
+#endif
+
+
enum armv7m_mode
{
ARMV7M_MODE_THREAD = 0,
struct armv7m_common
{
+ struct arm arm;
+
int common_magic;
struct reg_cache *core_cache;
enum armv7m_mode core_mode;
int exception_number;
struct swjdp_common swjdp_info;
+ uint32_t demcr;
+
/* Direct processor core register read and writes */
- int (*load_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
- int (*store_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
+ int (*load_core_reg_u32)(struct target *target,
+ enum armv7m_regtype type, uint32_t num, uint32_t *value);
+ int (*store_core_reg_u32)(struct target *target,
+ enum armv7m_regtype type, uint32_t num, uint32_t value);
+
/* register cache to processor synchronization */
int (*read_core_reg)(struct target *target, unsigned num);
int (*write_core_reg)(struct target *target, unsigned num);
static inline struct armv7m_common *
target_to_armv7m(struct target *target)
{
- return target->arch_info;
+ return container_of(target->arch_info, struct armv7m_common, arm);
+}
+
+static inline bool is_armv7m(struct armv7m_common *armv7m)
+{
+ return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
}
struct armv7m_algorithm
int armv7m_blank_check_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t* blank);
+int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
+
extern const struct command_registration armv7m_command_handlers[];
#endif /* ARMV7M_H */